A system and method is disclosed for predicting and comparing wear scenarios in a rail system. The method can include generating and running a contact model of the interaction between a rail and a train car to produce a simulated loading on the rail for a predetermined time period; generating and running a wear model based on the material properties and/or friction modifier properties of the rail using the simulated loading to produce a simulated wear profile of the rail for the predetermined time period; obtaining a grinding profile to be performed on the rail during the predetermined time period; and generating an updated rail profile by modifying the rail profile by the simulated wear profile and the grinding profile. The method can predict and compare crack growth over time, and provide a financial model and comparison of costs and benefits for different maintenance protocols for the rail system.

The present invention relates to a method for the theoretical analysis of a process apparatus through which fluid flows, wherein a theoretical, in particular numerical simulation of the apparatus or of at least one part of the apparatus is carried out, wherein at least one element of the apparatus which does not comprise concrete as a material is replaced in the theoretical simulation by at least one concrete element which is manufactured from concrete, and wherein a load analysis of the apparatus is carried out with the aid of the theoretical simulation.

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

A development support device includes a receiver that receives selection information about a degradation mechanism of a power storage device from a terminal device after user authentication of the terminal device, a simulation execution unit that simulates degradation of the power storage device by using the selected degradation mechanism based on the received selection information, and a transmitter that transmits a simulation result by the simulation execution unit or a simulation program executed in simulating the degradation of the power storage device to the terminal device.

A computer-implemented method for designing a mechanical product formed in one or more materials including obtaining inputs including a finite element model representing the mechanical product and having an initial value of design variables, one or more load cases, a corresponding load history for each load case, boundary conditions, fatigue properties of the one or more materials, and a fatigue calculation scheme. The method further includes computing a distribution of fatigue damage over the finite element model based on the inputs, computing a distribution of sets of fatigue damage sensitivities over the finite element model based on the computed distribution of fatigue damage, each fatigue damage sensitivity of each set approximating a derivative of the fatigue damage relative to a respective design variable, and updating the value of the design variables based on the fatigue damage sensitivities.

A method includes generating a 3D computer-coded model of a component and performing simulations on the model to determine an onset of gross plastic deformation in a plurality of regions of the component, wherein the model is stored in a computer-readable medium.

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.

The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.