A device and method for building life cycle sustainability assessment using probabilistic analysis method, the device and method being capable of assessing and predicting building life cycle sustainability, and a recording medium storing the method. The device includes: a first storage unit storing a reference environmental impact assessment value of a reference building, and first and second environmental impact coefficient groups; an input unit receiving area information, amounts of building materials and energy sources; a probability distribution calculating unit storing a set value, and deducing probability distributions of the building materials and the energy sources; a first arithmetic unit calculating probability distributions of first and second environmental impact assessment values, and a probability distribution of a life cycle environmental impact assessment value; and a first output unit deducing a probability distribution of an environmental impact index, and outputting the deduced probability distribution of the environmental impact index.

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

The present disclosure relates to a method and apparatus for modeling a photovoltaic power curve, and a computer device and a storage medium thereof. The method includes: acquiring photovoltaic data at various time points within a specified time period; dividing the photovoltaic data at the various time points into at least two photovoltaic data packets; and establishing, according to the respective photovoltaic data of the at least two photovoltaic data packets, packet photovoltaic power curves respectively corresponding to the at least two photovoltaic data packets. By the method, the photovoltaic data is fitted in different time periods during the photovoltaic curve modeling process, thereby reducing the influence of the difference between photoelectric conversion efficiencies in different time periods on photovoltaic curve modeling, and improving the accuracy of photovoltaic curve modeling.

Disclosed is a method and apparatus that determines receiver capacitance values for a receiver cell from a multi-segment receiver capacitance model (C1Cn) model. Values for receiver capacitance are determined from a Composite Current Source for Noise (CCSN) model under conditions used to attain receiver capacitance values for the C1Cn model Difference values for the difference between the values from the CCSN model and from the C1Cn model are determined. Calibration factors are iteratively applied to parameters of the CCSN model to obtain a minimum difference value for difference between receiver capacitance values from the CCSN model and receiver capacitance values from the C1Cn model. Calibration factor values that result in the difference value being within an acceptable range are stored.

A circuit breaker distribution system is configured to provide selective coordination. The system comprises a solid-state switch disposed as a main or upstream breaker and a switch with an over current protection disposed as a branch or downstream breaker. The microcontroller to: allow repeated pulses of current through to the branch or downstream breaker in an event of an overload or short circuit, choose a maximum current limit for the solid-state switch as a “chop level” such that the chop level is chosen higher than a rated current of the solid-state circuit breaker but low enough that the solid-state switch is not damaged from repeated pulses over a period of time needed to switch OFF the branch or downstream breaker and add a pulse interval after the current chops to zero but before the solid-state circuit breaker returns to an ON state for a next pulse to begin.

A fractional-order KiBaM battery model considering nonlinear capacity characteristics and a parameter identification method includes a temporary capacity portion and an available capacity portion for describing nonlinear capacity characteristics of a battery, wherein the temporary capacity portion represents the power that can be directly obtained during the discharge, indicating the state of charge (SOC) of the battery; the available capacity portion represents the power that cannot be directly obtained, and such two portions are connected; when the battery is discharged, the load current i flows out from the temporary capacity portion, and a power passing rate coefficient of such capacity portions is obtained; and the nonlinear capacity effect and recovery effect of the battery are denoted by the height ratio of the temporary capacity and available capacity portions in view of the magnitude of the fractional order of battery capacity characteristics.

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Techniques are provided for generating score(s) and/or correction(s) for a digital twin representing a utility network. One or more bridges transform data, from a plurality of system and associated with a utility network, to a different format, e.g., relational database format. A process generates a digital twin of the utility network utilizing the data in the different format. A data quality service (DQS) performs evaluations and/or analyses of the digital twin to generate a baseline score and an updated score representing a state of the digital twin if corrections are applied. If the updated score meets or is above a threshold value, the DQS automatically applies and save the corrections to the digital twin. If the updated score does not meet the threshold value, the DQS presents a failure notification and one or more graphical representations of the utility network such that incremental corrections can be made.

A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.