A method and device for training an energy management system in an on-board energy supply system simulation, includes: simulating a driving cycle having defined recuperation; plotting state variables of the on-board energy supply system; calculating a recuperation power from a recu-peration current and a battery voltage; producing input vectors for a neural network; producing a reward function; and training the neural network.

One embodiment provides a system and method for predicting network power usage associated with workloads. During operation, the system configures a simulator to simulate operations of a plurality of network components, which comprises embedding one or more event counters in each simulated network component. A respective event counter is configured to count a number of network-power-related events. The system collects, based on values of the event counters, network-power-related performance data associated with one or more sample workloads applied to the simulator; and trains a machine-learning model with the collected network-power-related performance data and characteristics of the sample workloads as training data 1, thereby facilitating prediction of network-power-related performance associated with a to-be-evaluated workload.

A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes acquiring, based on a compression model that is acquired by learning processing on a set of data generated by using a combination of values of variables and that compresses dimensions of data, a point corresponding to data generated by using a predetermined combination of the values of variables within a compressed space; acquiring, based on the point corresponding to the data generated by using the predetermined combination, a target point within the space corresponding to a target value of a characteristic changing in accordance with the values of variables, and a regression model within the space for a predetermined variable of variables, a change amount of the predetermined variable; and changing the value of the predetermined variable included in the predetermined combination by using the change amount.

A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

A circuit breaker distribution system is configured to provide selective coordination. The system comprises a solid-state switch disposed as a main or upstream breaker and a switch with an over current protection disposed as a branch or downstream breaker. The solid-state switch comprises a microcontroller including a processor and a memory, and computer-readable logic code stored in the memory which, when executed by the processor, causes the microcontroller to: allow repeated pulses of current through to the branch or downstream breaker in an event of an overload or short circuit, and choose a maximum current limit for the solid-state switch as a “chop level” such that the chop level is chosen higher than a rated current of the solid-state circuit breaker but low enough that the solid-state switch is not damaged from repeated pulses over a period of time needed to switch OFF the branch or downstream breaker.

A data processing apparatus that searches for a combination of values of a plurality of state variables by which a value of an Ising-type evaluation function including the plurality of state variables and a weight value, and that includes a memory and a processor. The memory stores group information indicating to which of a plurality of groups obtained by grouping the plurality of state variables each of the plurality of state variables belongs. The processor determines whether to allow a change in a value of each of a plurality of first state variables based on a comparison result between a predetermined value and a change amount of a value of the evaluation function, and change, when a change in values of a plurality of second state variables is allowed, values of the plurality of second state variables.

Predicting power usage of a chip may include receiving placement data describing a placement, within the chip, of a plurality of logical components of the chip; providing the placement data as an input to a neural network; and determining, by the neural network, based on the placement data, a predicted power usage of the chip.

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

A method (and system) includes receiving, at a computing device including a design tool application, design parameters indicative of a plurality of power supply loads to be powered. The method further includes generating power supply solutions that do not include multi-channel voltage regulators and generating power supply solutions that do include multi-channel voltage regulators. The method also includes ranking all power supply solutions and providing the ranked power supply solutions to a user.