A method for creating a photovoltaic system comprising several interconnected solar panels. The method includes the steps of generating an image of an installation site of the photovoltaic system; receiving, from a user, image coordinates corresponding to points on the image; defining an installation area of the solar panels using the image coordinates; receiving site-specific data of the installation site and solar panel specification data of one or more types of solar panels; and generating a layout of the solar panels within the installation area using the installation area, the site-specific data, and solar panel specification data.

In some embodiments, techniques for creating a design for a physical device are provided. A computing system receives an initial design of the physical device. Performance of the physical device is simulated using the initial design. A performance loss value is determined for the physical device based on the simulated performance at a target wavelength and one or more delta wavelengths. The performance loss value is backpropagated to determine a gradient corresponding to an influence of changes in the initial design on the total performance loss value. The initial design of the physical device is revised based at least in part on the gradient.

A method for checking electrical rules in a design of a circuit including transistors connected by nodes, includes defining a hierarchical database including (i) a root representing the circuit, and (ii) instances of context-cells representing design entities and including node-ports that connect the design entities. Electrical properties of the node-ports are propagated from the root through the node-ports to at least a portion of the context-cells. The electrical properties, which were propagated from the root, are propagated from one or more of the context-cells to one or more peer context-cells. An electrical rule violation in at least one of the context-cells is identified based on the propagated electrical properties.

A device for powering electronic devices comprises a thermoelectric generator (TEG) applied over a temperature gradient. A combination of feed forward and feed back control of the TEG unit allows for continued operation that is robust to reversal of the temperature gradient, for example over the duration of a diurnal cycle.

Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

An energy evaluation system includes an energy system modeling framework and an Application Program Interface (API) as part of the energy system evaluation framework. The energy evaluation system can be configured to query a simulation application program interface (API) with PV system configuration parameters as arguments, generate a shade loss time series based on the system configuration parameters, simulate energy output for the PV system based on the shade loss time series, and output energy aggregations based on the simulation.

The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

A system and method for automatically generating layout masks of power rails within redistribution layers of a semiconductor package are described. In various implementations, a user defines attributes to use for automatic power rail generation in the redistribution layers. The circuitry of a processor of a computing device used by the user executes instructions of a redistribution layer (RDL) automated power rail generator, which is referred to as the power rail generator. The power rail generator uses the attributes and a copy of the RDL netlist of the signal routes within the RDL to generate RDL mask layout data representing the signal routes of the power rails within the RDL. The processor generates the power rails for a significantly large number of signal routes in the RDL based on the received data such as the attributes that allow the user to customize the automatic generation.

Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.