A device may generate, using a random telegraph signal (RTS) noise generator, a simulated RTS noise as input to a transistor included in an electronic circuit. The device may determine, based on the simulated RTS noise input to the transistor, a simulated output signal from the transistor.

An arithmetic processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to execute a prediction process and a search process in an evolutionary calculation process for searching an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, wherein the prediction process includes predicting a range of an eigen solution for a second input, which satisfies a predetermined eigen solution condition, based on a first eigen solution for a first input when searches an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, and the search process includes searching a second eigen solution for the second input, which satisfies the eigen solution condition, in the predicted range of the eigen solution.

A high-fidelity, multi-point, full-mission sonic-boom propagation tool that includes functionality to handle aircraft trajectories and maneuvers, as well as, all relevant noise metrics at multiple points along the supersonic mission. This allows efficient computation of sonic-boom loudness across the entire supersonic mission to allow pilots and aircraft operators to plan the aircraft flight path to manage the sonic boom footprint.

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Disclosed is a robust topology optimization design method of a damping composite stiffened cylindrical shell box structure, comprising: constructing working load data, and obtaining circumferential target modal frequencies based on the working load data and the stiffened cylindrical shell box; laying constrained layer damping materials on the stiffened cylindrical shell box to construct a damping composite stiffened cylindrical shell box; constructing interval parameters based on the damping composite stiffened cylindrical shell box, and obtaining modal loss factor based on the interval parameters; constructing an objective function based on the modal loss factors, constructing design variables and constraint conditions based on the damping composite stiffened cylindrical shell box, integrating the objective function, design variables and constraint conditions to form an interval robust topology optimization model; updating the design variables based on the interval robust topology optimization model, and obtaining an optimized topology configuration of the damping composite stiffened cylindrical shell box.

A method for simulating interactions between a propagating field and occluding bodies in a volume is provided. The method includes using a processor to construct a three-dimensional grid structure having a plurality of cells, the volume containing a plurality of two-dimensional triangles that intersect or reside in one or more of the cells; to iterate through a plurality of rays and trace each ray of the plurality to approximate the propagating field; to determine and account for all interactions between each ray of the plurality and the occluding bodies, where the determining includes performing ray-triangle intersection for all triangles of the plurality of triangles intersecting or residing in cells occupied by the occluding bodies, and the accounting includes adding additional rays of the plurality of rays as reflections, transmissions, and diffractions of the approximated propagating field.

Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.