A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

A radiation risk assessment method and apparatus, an electronic device, and a storage medium. The method comprises: determining a risk signal to he assessed on the basis of a product design model, and determining whether the risk signal to be assessed is periodic (S101); if yes, determining a spectral amplitude corresponding to the risk signal to be assessed (S102); obtaining current intensity of a radiation source and the distance between the risk signal to be assessed and the radiation source (S103); calculating radiation intensity of the risk signal to be assessed by using the spectral amplitude, the current intensity, and the distance (S104); and determining a corresponding radiation risk assessment result according to the radiation intensity (S105). Radiation intensity of a risk signal to be assessed is calculated by using current intensity of a radiation source and the distance between the risk signal to be assessed and the radiation source, thereby achieving quantitative radiation risk assessment; moreover, the risk signal to be assessed is determined on the basis of a product design model, and thus radiation test can be carried out without waiting until the later period of product production, thereby effectively reducing labor and material resources consumed for later rectification due to high radiation risk.

Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

A simulation test system and method for vehicle road noise cancellation (RNC) are provided in one or more embodiments of the present disclosure. The simulation test system may include a vehicle RNC simulation system and a power amplifier. The vehicle RNC simulation system is configured to simulate an RNC system in a vehicle environment. The power amplifier is configured to execute an RNC algorithm and may perform data communication with the vehicle RNC simulation system. The vehicle RNC simulation system transmits acceleration data representing an acceleration signal and microphone data representing a microphone signal to the power amplifier as inputs to the RNC algorithm in the power amplifier. Moreover, the vehicle RNC simulation system may receive speaker data representing a speaker signal from the power amplifier. The vehicle RNC simulation system includes a secondary path simulation model and a signal flow simulation model.

A non-transitory computer-readable storage medium storing an electromagnetic field analysis program that causes at least one computer to execute a process, the process includes specifying a dimension of a width of wiring included in first circuit information and a dimension of a thickness of the wiring; generating second circuit information obtained by changing value of one selected from the dimension of the width and the dimension of the thickness to zero based on a ratio between the dimension of the width and the dimension of the thickness; and executing an electromagnetic field analysis based on the second circuit information.

According to one embodiment, a method for designing a semiconductor integrated circuit acquires a first simulation result by circuit simulation including a first kind of parasitic element and a second kind of parasitic element to be evaluated for a first net and a second net. A net selection circuit is generated including just one kind of parasitic element on one net selected from the first net and the second net and the two kinds of parasitic elements on the other nets, and a net selection simulation result is acquired by circuit simulation for each of the net selection circuits.

An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

A method is provided. The method includes: obtaining a parameter value of a determined dimension parameter, an initial parameter value of a dimension parameter to be optimized, and a target capacitance value of an interdigital capacitor; partitioning a geometric structure of the interdigital capacitor to obtain a plurality of sections of the interdigital capacitor, where the plurality of sections are in a one-to-one correspondence with a plurality of coplanar multiple-transmission line models; obtaining a capacitance value expression of the interdigital capacitor based on the plurality of coplanar multiple-transmission line models; determining, based on the parameter value of the determined dimension parameter, the target capacitance value, and the capacitance value expression of the interdigital capacitor, a loss function including the dimension parameter to be optimized; and optimizing, based on the initial parameter value by minimizing the loss function, the parameter value of the dimension parameter to be optimized.

The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.

A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.