Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

A system and method generates a compensation circuit element for an optical circuit design by receiving an optical circuit design. The optical circuit design includes optical circuit elements and channels optically connecting the optical circuit elements. Further, a first compensation length for a first channel of the channels is determined based on a first measured length parameter of the first channel and a first design length parameter associated with the first channel. A compensation circuit element is determined based on the first compensation length. An updated optical circuit design is determined based on the compensation circuit element.

A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one current cell will have to be moved in order to place the ECO cell in the target region. Timing slacks for current cells in a neighborhood of the target region are determined. Based on the timing slacks of the current cells, at least one of the current cells is moved to a different location to create sufficient open space to place the ECO cell within the target region.

An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.

A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

A method performed by at least one processor includes the following steps. A layout of an integrated circuit (IC) is accessed, wherein the layout has at least one cell. A context group for the cell is determined based on a layout context of the cell, wherein the context group is associated with a timing table. A timing analysis is performed on the layout to determine whether the layout complies with a timing constraint rule according to the timing table. A system including one or more processors including instructions for implementing the method and a non-transitory computer readable storage medium including instructions for implementing the method are also provided.

A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.

A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

A multi-stage FPGA routing method for optimizing time division multiplexing comprises the following steps: S1: collecting an FPGA set, an FPGA connection pair set, a net set and a net group set; S2: acquiring a routing topology of each net according to the FPGA set, the FPGA connection pair set, the net set and the net group set under the condition where TRs are not assigned; S3: assigning a corresponding TR to each edge of each net according to different delay of each net group; and S4: performing TR reduction and edge validation cyclically, iteratively optimizing net groups with TR being greater than a preset value until iteration end conditions are met, so as to obtain an optimal routing result. The multi-stage FPGA routing method may optimize the delay of inter-chip signals of a multi-FPGA prototype system and guarantee the routability of the multi-FPGA prototype system.