Embodiments of the disclosure provide a method for synchronizing a first module and a second module of a logic system design, wherein the first module and the second module operate according to a system clock, the first module includes a plurality of sub-modules, the method comprising: determining, among the plurality of sub-modules, whether a target sub-module generates an event indication; in response to determining that the target sub-module generates the event indication, switching a period of the system clock from a first clock period to a second clock period, wherein the first clock period is less than the second clock period; and running the target sub-module according to the second clock period.

A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode, determining a plurality of second paths that are to be tested in a function mode, determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode, and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer.

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.

A method of operating a computing device for detecting clock domain crossing (CDC) violation in a design of a memory device, the method includes parsing a Netlist to generate a circuit database, parsing a clock tree using the circuit database to generate a clock tree database, extracting a non-toggled point using the clock tree database to generate a false path database based on the non-toggled point, and extracting a CDC violation identified from one or more simulation waveforms using the clock tree database and the false path database.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then estimated based on applying the EICW.

Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.

The invention relates to the technical field of computer-aided design of integrated circuits, and provides a two-step X-architecture Steiner minimum tree construction method for very large scale integration (VLSI). Based on the advantages of an X-architecture model and a particle swarm optimization technique, the method is implemented through two steps: (1) the stage of social learning discrete particle swarm search, which comprises: using an edge-vertex encoding strategy capable of maintaining optimal topological information of particles, designing a fitness function taking wirelength into consideration; and using a chaotic decreasing mutation strategy and a new social learning strategy to design a new discrete particle swarm update formula; and (2) a stage of wirelength optimization, which comprises: designing a local topological optimization strategy to minimize the wirelength of an X-architecture Steiner tree. The method guarantees short total wirelength of nets and has high stability, thus being able to construct a high-quality X-architecture Steiner minimum tree.