Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant k.sup.th difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant k.sup.th difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

Aspects of the invention include systems and methods for to detecting security vulnerabilities using modeled attribute propagation. A non-limited example of a computer-implemented method includes generating a model of a device under test, the model comprising a data path similar to the device under test and an attribute network. The method further includes detecting protected data that is introduced into the model and marking the protected data with an attribute. An end point of the marked protected data is detected along the data path. In response to the end point being indicative of a vulnerability, an alert is issued.

An embodiment may involve obtaining a specification of connectivity between a plurality of electronic components, a property library of logical validations, and a set of restrictions for an execution environment of the electronic components, wherein each of the electronic components is associated with at least one of the logical validations; determining that, according to properties in the property library applied to their associated electronic components, a subset of the electronic components exhibit invariance within the execution environment; based on the subset of the electronic components that exhibit invariance within the execution environment, rewiring the connectivity between the plurality of electronic components; and performing logic synthesis on the connectivity between the plurality of electronic components as rewired to simplify at least some of the subset of the electronic components that exhibit invariance within the execution environment.

In various embodiments, a style comparison application compares geometric styles of different three dimensional (3D) computer-aided design (CAD) objects. In operation, the style comparison application executes a trained neural network one or more times to map 3D CAD objects to feature map sets. The style comparison application computes a first set of style signals based on a first feature set included in the feature map sets. The style comparison application computes a second set of style signals based on a second feature set included in the feature map sets. Based on the first set of style signals and the second set of style signals, the style comparison application determines a value for a style comparison metric. The value for the style comparison metric quantifies a similarity or a dissimilarity in geometric style between a first 3D CAD object and a second 3D CAD object.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).