This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.

A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

A simulation method, simulation device and a readable storage medium are disclosed, in which a correction circuit is added to an equivalent circuit model for a three-terminal circuit employed in a SPICE simulation system. The correction circuit enables simulating behavior of the resistor module, enabling the SPICE simulation system to take in account the body effect. Therefore, simulation results obtained from the simulation model and simulation parameters for the resistor module can better reflect resistor behavior with body effect in an actual circuit, resulting in effectively improved simulation accuracy of the SPICE simulation system and allowing the system to provide more accurate circuit simulation results. Fitting tests can be performed to obtain first-order, second-order and resistor-width-dependent correction coefficients for a body voltage of the resistor module. Thus dependence of resistor behavior on the body voltage can be better predicted, allowing a good reflection of resistor behavior with body effect.

The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.

A method and/or system is disclosed for pre-silicon verification of a first integrated circuit design modified to a second integrated circuit design to avoid a hit of property P where property P has a known counterexample. The method/system includes applying a first implication check in an equivalence testbench on the first integrated circuit and on the second integrated circuit to determine whether the second integrated circuit hits property P in the same way as the first integrated circuit hits property P. Additionally or alternatively applying a second implication check to determine whether the second integrated circuit hits property P at a different timestep than the first integrated circuit hits property P. Additionally or alternatively applying a third implication check to determine whether the second integrated circuit hits property P further along a path than the first integrated circuit hits property P.

Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Techniques and systems for classifying non-detected faults (NDFs) in a formal verification test-bench are described. A sequential equivalence checking formulation can be constructed based on an integrated circuit (IC) design and a set of NDFs, wherein the set of NDFs do not falsify a first set of properties of the IC design, wherein said constructing the sequential equivalence checking formulation comprises creating a second set of properties based on the set of NDFs, wherein each property in the second set of properties corresponds to an NDF in the set of NDFs. A formal sequential equivalence checking tool can be used to prove the second set of properties in the sequential equivalence checking formulation. Next, for each property in the second set of properties that is disproven by the formal sequential equivalence checking tool, some embodiments can classify a corresponding NDF in the set of NDFs as an observable NDF.

A system and method for input-directed constrained random simulation includes obtaining an initial state for a finite state machine (FSM) that models an electronic circuit design under test (DUT), the initial state assigning values to registers of the device under test, by providing an initial state function I(s) relating to the FSM to a satisfiability problem (SAT) solver to obtain register values that satisfy the initial state function. A random Boolean circuit R(i) is constructed. A SAT solver is queried for a satisfying assignment for a conjoined expression providing the conjunction of at least a valid-transition Boolean circuit T(s, i, s) and the random Boolean circuit R(i), the valid-transition Boolean circuit describing valid transitions of the FSM as a function of current state s, inputs i, and next state s. The satisfying assignment is added to the end of a constructed trace.

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant k.sup.th difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.