Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.

A method for performing a rewind functional verification includes identifying state variables that model a number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and a direction of a register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the retimed design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x.sub.0.sup.t.sup.0? . . . ?x.sub.n.sup.t.sup.n, wherein t.sub.0 . . . t.sub.n are fixed, rational numbers, x.sub.0 . . . x.sub.n are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X.sub.0, . . . , X.sub.n and any second non-exception input set Y=Y.sub.0, . . . , Y.sub.n in an input space wherein corresponding inputs have a same mantissa and (t.sub.0X.sub.0.exp+ . . . +t.sub.nX.sub.n.exp)?(t.sub.0Y.sub.0.exp+ . . . +t.sub.nY.sub.n.exp) is an integer, an instantiation of the hardware design generates outputs X and Y with a same mantissa and X.sub.exp?(t.sub.0X.sub.0.exp+ . . . +t.sub.nX.sub.n.exp)=Y.sub.exp?(t.sub.0Y.sub.0.exp+ . . . +t.sub.nY.sub.n.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t.sub.0X.sub.0.exp+ . . . +t.sub.nX.sub.n.exp)?(t.sub.0Y.sub.0.exp+ . . . +t.sub.nY.sub.n.exp) is an integer.

A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

Apparatus and associated methods relate to fitting a virtual mask to a virtual face by first fitting a chin region of the virtual mask to the virtual face, then determining an virtual mask angle that maintains the fitted chin region while simultaneously fitting a nose-bridge region of the virtual mask to the virtual face, and then calculating a fit-quality metric corresponding to the fitted position. In an illustrative embodiment, the fitted chin region may include the high curvature menton region of the chin. In some examples, a virtual mask may be virtually pressed toward the virtual face using a predetermined force corresponding to a force of a mask securing device of a real mask corresponding to the virtual mask In an exemplary embodiment, the fitting of a virtual mask to a virtual face may advantageously yield a mask's fit quality in a brief amount of time.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each of the first and second hardware design models, at least one specific output value for each of the plurality of initial states. Hardware processor(s) are used for selecting the corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model.

Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.