A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

A method for performing rewind functional verification includes identifying state variables that model the number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant k.sup.th difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the k.sup.th difference is predetermined and e is equal to k+1 when the value of the k.sup.th difference is not predetermined.

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant k.sup.th difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Embodiments herein describe performing an engineering change order (ECO) after a physical design team has begun (or finished) a physical design (PD) netlist. However, the ECO may describe changes or additions to the logic and/or nets using component names found in a design netlist that is different than the PD netlist. Embodiments herein rely on generating an equivalents nets file that the maps the components in the design netlist to the components in the PD netlist. When performing an ECO, the PD team can use this file to map the components in the ECO (which are based on the design netlist) to all the equivalent components in the PD netlist. The PD team then selects one of the equivalent components to alter as indicated in the ECO.

A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

A method, system, and a computer readable medium enables determining a design layout of a battery that includes an electrical arrangement of one or more battery cells and one or more electrical components. The method also includes determining operational parameters of a batch of battery cells and electrical components to potentially be used in the battery and selecting at least one battery cell and at least one electrical component for the electrical arrangement of the design layout. The method further includes comparing the operational parameters of the at least one battery cell and at least one electrical component and determining that the operational parameters of the at least one battery cell and at least one electrical component are within a predetermined threshold. The method includes selecting the at least one battery cell and at least one electrical component as a potential combination for the design.

Embodiments herein describe performing an engineering change order (ECO) after a physical design team has begun (or finished) a physical design (PD) netlist. However, the ECO may describe changes or additions to the logic and/or nets using component names found in a design netlist that is different than the PD netlist. Embodiments herein rely on generating an equivalents nets file that the maps the components in the design netlist to the components in the PD netlist. When performing an ECO, the PD team can use this file to map the components in the ECO (which are based on the design netlist) to all the equivalent components in the PD netlist. The PD team then selects one of the equivalent components to alter as indicated in the ECO.