A method for generating computer-readable instructions to automatically generate a three-dimensional architectural model including: receiving a human-readable text file comprising a description of functional elements of a structure, parsing the text file to identify keywords comprised by the text file, generating a plurality of datasets responsive to the key words; generating instructions to create level objects responsive to the datasets, instructions to create floor objects responsive to the datasets and the level objects, instructions to create exterior wall objects responsive to the plurality of datasets and the one or more level objects, instructions to create interior wall objects responsive to the and level objects, instructions to create room objects responsive to the datasets, level objects, exterior wall objects, and interior wall objects, and providing the instructions to architectural modeling software.

A method, according to some implementations, receiving, for each trial design of a set of trial designs, a simulated performance and presenting, for at least two criteria, a plot of the simulated performance. The method may further include presenting, for at least one additional criteria, a plurality of contour lines on the plot and selecting a subset of the set of trial designs based on the plurality of contour lines.

A method and apparatus for manufacturing a part. The part is designed using a CAD system to generate a CAD part model of the part. Features of the part are identified from the CAD part model of the part. A parametric specification of the part is generated using the features of the part. The parametric specification of the part is saved as a parametric part model. The parametric part model is used to fabricate the part.

A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.

A W-graph system comprising a server connected with a plurality of clients via a network. Each client/user performs a design task via a design application while the server collects timestamped event data. The server generates a plurality of W-graphs for a plurality of tasks based on the collected event data. Each W-graph comprises one or more representative workflows, each representative workflow comprising at least one merged node representing nodes from different workflows for different users performing the same task. A W-graph for a task selected by the user may be viewed in a W-graph GUI. A user may also select a W-suggest function to have a current workflow for a task analyzed for optimization based on a W-graph generated for the same task. A modified current workflow is generated that highlights user techniques in the current workflow that are less efficient than user techniques in the W-graph.

Embodiments herein describe UAVs that utilize tail boom assemblies from pre-existing aircraft designs as lift generating elements. In one embodiment, a UAV includes a fuselage having a first end and a second end opposite the first end, a first tail boom coupler disposed at the first end, and a second tail boom coupler disposed at the second end. Each of the first tail boom coupler and the second tail boom coupler are configured to mechanically couple with a plurality of tail boom assemblies procured from a pre-existing aircraft design.

An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.

Methods, apparatus, systems, and articles of manufacture are disclosed for designing hardware. An example apparatus includes processor circuitry to execute machine readable instructions to determine a first hardware architectural configuration of a hardware component based on a design constraint, simulate an execution of the first hardware architectural configuration for a plurality of workloads to generate a respective plurality of objective design spaces, the objective design spaces based on one or more objectives; generate an aggregate score by aggregating a plurality of design space performance indicators, ones of the plurality of design space performance indicators corresponding to respective ones of the plurality of objective design spaces; search a design database based on the aggregate score to identify a second hardware architectural configuration, and predict a performance of the second hardware architectural configuration to generate a performance metric by executing a proxy function corresponding to the second hardware architectural configuration.

Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.