A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.

Provided is a method of detecting a defective layer. A method, performed by a computing system, of detecting a defective layer of a semiconductor device including a plurality of layers includes obtaining candidate defective layer information regarding a plurality of candidate defective layers and obtaining physical structure information regarding the candidate defective layers, dividing each of wires in the candidate defective layers into virtual micro areas based on the candidate defective layer information and based on the physical structure information, and identifying a defective layer from among the candidate defective layers according to a number of the virtual micro areas.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

The present disclosure relates to a computer-implemented method for simulation of an integrated circuit for yield analysis of the integrated circuit, the method comprising the steps of: a) for a plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of the integrated circuits; b) selecting at least one sample from each initial sampling set randomly and combining the selected samples into an initial simulation set; c) running an initial simulation of an operation of the integrated circuit, applying the initial simulation set, wherein the operation has a criterion for passing and failing the operation; d) if the initial simulation fails: storing the samples of the initial simulation set into initial sampling distributions for each variable; e) repeating steps b)-d) until a sufficient number of failures have been obtained; f) building an importance sampling distribution based on each initial sampling distribution, the importance sampling distribution having a lower portion, a center portion and an upper portion; g) generating a secondary simulation set by drawing a number of samples from the importance sampling distribution for each variable; h) simulating the integrated circuit by applying the secondary simulation set; i) repeating steps g)-h) a number of times; j) mapping of the resulting yields to the provided distributions, thereby obtaining a yield of the integrated circuit.

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

A global computer aided engineering (CAE) model representing an electronic product that contains solder joints and an individual detailed solder joint model are received. The solder joint model can include a solder ball, one or more metal pads, a portion of printed circuit board, and a portion of semiconductor chip component. The global CAE model includes locations of the solder joints to be evaluated in a drop test simulation. The solder joint model is replicated at each location to create a local CAE model via a geometric relationship between the global CAE model and the local CAE model. Simulated physical behaviors of the product under a design condition are obtained in a co-simulation using the global CAE model in a first time scale and the local CAE model in a second time scale. Simulated physical behaviors are periodically synchronized based on kinematic and force constraints.

A method for path routing according to an embodiment of the present disclosure may include selecting a first start point and a first end point with which path routing is performed in a circular frame generated by connecting all points included in one or more start point sets included in a layer, one or more end point sets paired with the start point set, and one or more edge point pair sets to one closed curve, generating a connectivity graph by connecting edge points included in one or more nodes corresponding to segments obtained by dividing the circular frame into one or more regions, and connecting the first start point and the first end point based on a cost for connecting the first start point and the first end point calculated using the connectivity graph.

A computer-implemented method for simulation of an integrated circuit for yield analysis includes: a) for plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of circuits; b) selecting at least one sample from each initial set randomly and combining into initial simulation set; c) running initial simulation of operation of circuit, applying initial simulation set, the operation having passing/failing criterion; d) if fails: storing samples of initial set into initial sampling distributions for each variable; e) repeating steps b)-d) until sufficient failures obtained; f) building importance sampling distribution based on each initial sampling distribution, the importance distribution having lower, center, upper portions; g) generating secondary simulation set by drawing samples from importance sampling distribution for each variable; h) simulating circuit by applying the secondary set; i) repeating steps g)-h); j) mapping resulting yields to provided distributions, to obtain a yield.

A method for predicting yield relating to a process of manufacturing semiconductor devices on a substrate, the method including: obtaining a trained first model which translates modeled parameters into a yield parameter, the modeled parameters including: a) a geometrical parameter associated with one or more selected from: a geometric characteristic, dimension or position of a device element manufactured by the process and b) a trained free parameter; obtaining process parameter data including data regarding a process parameter characterizing the process; converting the process parameter data into values of the geometrical parameter; and predicting the yield parameter using the trained first model and the values of the geometrical parameter.