A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

An electronic control unit for controlling and/or regulating at least one motor vehicle includes at least one integrated microcontroller system for executing software and at least two microcontroller units that each executes at least one independent operating system. The at least one interface is provided for the purpose of interchanging information between the microcontroller units. The electronic control unit includes a first microcontroller unit configured to control and/or regulate of a first motor vehicle system, and a second microcontroller unit configured to use the interface of the first microcontroller unit to provide defaults for the control and/or regulation of the first motor vehicle system.

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.

A recovery site is configured to process a task using a copy of an original file associated with the task. The original file is stored on a production site, and a copy of the original file is stored on a recovery site. The task is determined to be suitable for processing on the recovery site based on the task comprising reading the file, the task completable without user input, the task not requiring a physical location for processing, and the task not altering the copy of the original file. The original file is determined to match the copy of the original file based on a modification time associated with the original file being earlier than a copy time associated with the copy of the original file. The task is processed on the recovery site using the copy of the original file, and at least one result file is output.

Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

Methods that copy data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays are provided. One method includes requesting a subset of the data from a backup system mirroring the set of data at a remote location in response to detecting an error in a storage device of an array of primary storage devices storing a set of data. The method further includes receiving the subset of the data from the backup system and storing the subset of the data in an array of auxiliary storage devices co-located with the array of primary storage devices in which the subset of the data can correspond to data stored on the storage device. Systems and computer program products for performing the above method are also provided.

An information handling system and method allows implementation of fault-tolerant storage subsystems using multiple storage controllers not themselves originally designed to support the redundancy of such fault-tolerant storage subsystems. In accordance with one embodiment, uncommitted data is efficiently and rapidly replicated across multiple commodity storage controllers, enabling faster and less expensive fault-tolerant storage subsystems. A redundant storage controller system using non-redundant storage controllers can improve the efficiency of data replication while providing failure protection against controller failure. A redundant storage controller system using non-redundant storage controllers and shared memory commonly accessible to the storage controllers can be enhanced to replicate data within host memory regions to protect against non-volatile memory failure. In accordance with at least one embodiment, an efficient data replication mechanism can be provided between storage controllers using off-the-shelf hardware.

A chassis may include a plurality of power supply units and a controller. The power supply units may be configured to deliver electrical energy to information handling resources disposed in the chassis. The controller may be communicatively coupled to the power supply units and configured to: receive operational parameters associated with the plurality of power supply units; receive user configuration parameters governing operation of components of the chassis; and based at least on the operational parameters and the user configuration parameters, determine if the controller and the plurality of power supply units are capable of operating in an enhanced power performance mode, wherein when operating in the enhanced power performance mode, one or more power supply units that would otherwise operate as idle redundant power supplies in absence of the enhanced power performance mode are oversubscribed to allocate electrical energy to the information handling resources disposed in the chassis.

System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface.