A query engine or compute engine receiving a query request identifies a plurality of data sources for satisfying a query request, and determines, from among multiple data sources, one or more fields likely to incur substantial computational demands in processing the query request. Pre-positioning aggregation logic moves the determined fields one data source to another data source for positioning the moved fields to a single data source from which the query result will be computed.

An arrangement for redundant data processing has an integrated circuit in which the functionality of a multi-core processor is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program. The results which emerge from the execution of the useful program by the different processor cores are compared by a comparison module of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) that is assigned to the particular processor core. In terms of hardware, the individual processor cores are at least partially implemented separately in the integrated circuit.

Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

A storage apparatus includes a plurality of drives and has a parity group constituted by a plurality of drives. The storage apparatus stores a hash management table to manage hash values of a prescribed data unit of data of the drives constituting the parity group and a hash value of a prescribed data unit of data stored in another drive other than the drives constituting the parity group. A processor is configured to determine whether a same data unit as a data unit included in data stored in a replacement target drive exists in the other drive on a basis of the hash values, and copy the same data unit of the other drive to a replacement destination drive when the same data unit exists.

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.