G06F2201/845

COPYING DATA FROM MIRRORED STORAGE TO AUXILIARY STORAGE ARRAYS CO-LOCATED WITH PRIMARY STORAGE ARRAYS
20190377649 · 2019-12-12 ·

Methods that copy data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays are provided. One method includes requesting a subset of the data from a backup system mirroring the set of data at a remote location in response to detecting an error in a storage device of an array of primary storage devices storing a set of data. The method further includes receiving the subset of the data from the backup system and storing the subset of the data in an array of auxiliary storage devices co-located with the array of primary storage devices in which the subset of the data can correspond to data stored on the storage device. Systems and computer program products for performing the above method are also provided.

CONFIGURABLE HYPERCONVERGED MULTI-TENANT STORAGE SYSTEM
20190369885 · 2019-12-05 ·

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

NETWORK AUTHENTICATION FOR A MULTI-NODE ARRAY
20190356736 · 2019-11-21 ·

A method of operating a storage system is provided. The method includes establishing a security context between a client and the storage system, the security context comprising a single ticket for multiple nodes within the storage system. The method includes distributing a first request to a first blade within the storage system and distributing a second request to a second blade within the storage system. The distributing the first request and the second request includes determining a node for handling the first request and the second request based on data within the single ticket.

System recovery using a failover processor

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

ERROR DETECTION USING VECTOR PROCESSING CIRCUITRY

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

Configurable computer memory

A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

Copying data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays

Methods that copy data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays are provided. One method includes requesting a subset of the data from a backup system mirroring the set of data at a remote location in response to detecting an error in a storage device of an array of primary storage devices storing a set of data. The method further includes receiving the subset of the data from the backup system and storing the subset of the data in an array of auxiliary storage devices co-located with the array of primary storage devices in which the subset of the data can correspond to data stored on the storage device. Systems and computer program products for performing the above method are also provided.

Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting

An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

CONFIGURABLE COMPUTER MEMORY
20190278708 · 2019-09-12 ·

A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

DYNAMIC SUPPRESSION OF ERROR DETECTION IN PROCESSOR SWITCH FABRIC
20190266060 · 2019-08-29 ·

A processing system tags read and write transaction packets that are functionally safe and suppresses redundant processing and error checking for functionally safe tagged transaction packets. The processing system includes compute elements that are interconnected via an interconnect fabric that includes resources to route operations. The interconnect fabric includes redundant resources to execute the same routing operations and comparator elements to indicate an error in response to detecting a mismatch between the output of a resource and its corresponding duplicate resource. The interconnect fabric selectively activates the duplicate resources and comparator elements in response to a tag associated with a transaction packet indicating that the transaction packet is safety-critical.