A method for efficient reads by reconstruction may determining an expected read latency for reading data from a primary read location of a plurality of storage devices, determining an expected reconstruction latency for reconstructing the data using reconstruction data, wherein portions of the reconstruction data are stored at a plurality of alternative read locations of the plurality of storage devices, reading the portions of the reconstruction data from the plurality of alternative read locations of the plurality of storage devices, and reconstructing the data stored at the primary read location using the reconstruction data, wherein the expected reconstruction latency is lower than the expected read latency.

A processor sets the size of a processor cache based on an identified workload executing at the processor. The cache size is set in response to the processor exiting a low-power mode. By setting the size of the cache based on the workload, the processor is able to tailor the size of the cache to the characteristics of a particular workload while also reducing, for at least some workloads, the overhead associated with entering or exiting the low-power mode.

Technologies for managing configuration-free platform firmware include a compute device, which further includes a management controller. The management controller is to receive a system configuration request to access a system configuration parameter of the compute device and access the system configuration parameter in response to a receipt of the system configuration request.

A performance manager (400, 500) and a method (200) performed thereby are provided, for managing the performance of a logical server of a data center. The data center comprises at least one memory pool in which a memory block has been allocated to the logical server. The method (200) comprises determining (230) performance characteristics associated with a first portion of the memory block, comprised in a first memory unit of the at least one memory pool; and identifying (240) a second portion of the memory block, comprised in a second memory unit of the at least one memory pool, to which data of the first portion of the memory block may be migrated to apply performance characteristics associated with the second portion. The method (200) further comprises initiating migration (250) of the data to the second portion of the memory block.

A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

A memory controlling apparatus is connected between computing nodes and memory modules. A cache module includes a cache shared by the computing nodes, and a coherence module manages coherence of the cache. Monitoring modules correspond to the memory modules, respectively, and monitors memory traffics of the memory modules, respectively. An address translation module translates an address of a request from the coherence module into an address of a corresponding memory module among the plurality of memory modules. When a cache line replacement request occurs, the coherence module selects a cache line replacement policy based on a result of comparing memory traffic in a target monitoring module during a predetermined period with a threshold, and replace a cache line based on the selected cache line replacement policy.

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

An apparatus comprises a processing device configured to monitor a storage cache storing a plurality of cache pages to determine whether the storage cache reaches one or more designated conditions and to determine cache replacement scores for at least a subset of the cache pages, the cache replacement scores being determined based at least in part on input-output access types for data stored in the cache pages. The processing device is also configured to select, responsive to determining that the storage cache has reached at least one of the one or more designated conditions, at least one of the cache pages to move from the storage cache to a storage device based at least in part on the determined cache replacement scores. The processing device is further configured to move the selected at least one of the plurality of cache pages from the storage cache to the storage device.