Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.

Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points. A method of operating a memory device may include writing data in the static cache if the static cache is available, and writing the data in the dynamic cache if the static cache is unavailable.

Systems and methods for improved process caching through iterative feedback are disclosed. In embodiments, a computer implemented method comprises retrieving updated metadata of a process to be executed, wherein the updated metadata includes information regarding cache misses from a prior execution of the process; automatically modifying a setting of a data stream control register based on the updated metadata; automatically setting a hint at a data cache block touch module; performing an initial execution of the process after the steps of retrieving the updated metadata, automatically modifying the setting of the data stream control register, and automatically setting the hint at the data cache block touch module; and modifying the updated metadata of the process after the execution of the process based on cache miss statistical data gathered during the execution of the process, to produce newly updated metadata.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

A method, system, and program product for implementing intelligent cache preloading is provided. The method includes monitoring current usage of a system of record (SOR) system. Historical data associated with historical usage of the SOR system is retrieved and analyzed based on the current usage. A ranked list of data items configured to be loaded within a cache structure of the cache system is generated and currently requested data items from the SOR system are loaded into the cache structure via a throttling process. A malfunction associated with operation of the SOR system is detected and access to the currently requested data items is enabled. The currently requested data items are organized within the cache structure in accordance with an order of the ranked list and access to the currently requested data items is enabled, during the malfunction, in accordance with the order of the ranked list.

A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

Embodiments of the present disclosure relate to a method and apparatus for managing cache. The method comprises determining a cache flush time period of the cache for a lower-layer storage device associated with the cache. The method further comprises: in response to a length of the cache flush time period being longer than a threshold length of time, in response to receiving a write request, determining whether data associated with the write request has been stored into the cache. The method further comprises: in response to a miss of the data in the cache, storing the write request and the data in the cache without returning a write completion message for the write request.

Systems and methods for cache optimization are disclosed. A request for a user interface is received from a first user device. The request includes a user key. An interface key corresponding to an interface template of the requested user interface is generated from the user key. The interface template of the requested user interface is loaded. The interface template includes one or more edge side include (ESI) identifiers in the interface template. An element key corresponding to a first ESI element associated with a first of the one or more ESI identifiers is generated from the user key. The first ESI element is loaded and positioned at a location within the interface template identified by the first of the one or more ESI identifiers. A complete user interface is provided to the first user device. The complete user interface includes the interface template having the first ESI element positioned therein.

A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.

Provided herein may be a storage device configured to perform a cache read operation by each memory device. The storage device may include a plurality of memory devices each including a plurality of memory blocks, and a memory controller configured to store and set cache setting information for each of the plurality of memory device, and control the plurality of memory devices such that, as a read operation on a select one of the plurality of memory devices, one of a cache read operation and a normal read operation is performed based on the cache setting information set for of the select memory device.