Embodiments for optimizing dynamic resource allocations in a disaggregated computing environment. A new workload is assigned to a subset of a plurality of processors, the subset of processors assigned a subset of a plurality of cache devices. A determination is made that the new workload is categorized as a cache-friendly workload having a memory need which can be met primarily by the subset of cache devices by identifying that underlying data necessitated by the new workload resides primarily within the subset of cache devices. Pursuant to determining the new workload is the cache-friendly workload, a cache related action is performed to increase performance of the new workload executed by the subset of processors and commensurately executes additional workloads performed by other ones of the plurality of processors within the disaggregated computing environment.

A tracing coprocessor that records execution trace data based on a cache coherency protocol (CCP) message. The tracing coprocessor comprises logic that causes the tracing coprocessor to listen on a bus that is communicatively coupled to a primary processor that executes executable code instructions. The logic also causes the tracing coprocessor to, based on listening on the bus, identify at least one CCP message relating to activity at a processor cache. The logic also causes the tracing coprocessor to identify, from the at least one CCP message, a memory cell consumption by the primary processor. The logic also causes the tracing coprocessor to initiate logging, into an execution trace, at least a memory cell data value consumed by the primary processor in connection with execution of at least one executable code instruction.

Technologies for providing efficient pooling for a system that includes a hyper converged infrastructure. A sled of the system includes a network interface controller that includes a first bridge logic unit to communicatively couple to a network of bridge logic units. The first bridge logic unit is further to obtain, from a requestor device, a request to access a requested device, determine whether the requested device is on the present sled or on a remote sled different from the present sled, selectively power on, in response to a determination that the requested device is located on the present sled, the requested device, communicate, in response to a determination that the requested device is on the remote sled, with a second bridge logic unit of the remote sled, and provide, to the requestor device through the first bridge logic unit, access to the requested device.

Performance optimization is achieved by clarifying cache usage characteristics of each application from usage conditions of physical resources (caches) in real time and automatically controlling the cache usage amount of each application. Thus, a system includes a main memory to and from which data is written and read, a level 3 cache memory which can be accessed faster than the main memory, a CPU core configured to execute processing by performing write and read to and from the memory and the cache, a usage amount measurement unit configured to measure a usage condition of a cache of each virtual machine (13a to 13c) executed by the CPU core, an allocation amount calculation unit configured to calculate cache capacity to be allocated to each virtual machine (13a to 13c) from the usage condition, and a control unit configured to allocate the cache capacity to each virtual machine (13a to 13c).

Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.

A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

A technology for estimating one or more cache hit rates. An implementation includes receiving a request-response pair, calculating a fingerprint for the request-response pair, storing the fingerprint, and determining whether the fingerprint is a member of a bloom filter.

A method in one embodiment comprises separating logical block addresses of one or more storage devices of a storage system into a plurality of ranges of logical block addresses using a designated chunk size, the chunk size denoting a particular number of logical block addresses. The method further comprises assigning different ones of the ranges of logical block addresses to different ones of a plurality of cache entities of the storage system, to select paths for delivery of respective input-output operations from a host device to the storage system based at least in part on the assigning, detecting particular ones of the input-output operations that each overlap with two or more adjacent ranges of the plurality of ranges, and responsive to the detected input-output operations exceeding a threshold, modifying the chunk size and repeating at least portions of the separating, assigning, selecting and detecting utilizing the modified chunk size.

Introduced herein is a technique that uses ML to autonomously find a cache management policy that achieves an optimal execution of a given workload of an application. Leveraging ML such as reinforcement learning, the technique trains an agent in an ML environment over multiple episodes of a stabilization process. For each time step in these training episodes, the agent executes the application while making an incremental change to the current policy, i.e., cache-residency statuses of memory address space associated with the workload, until the application can be executed at a stable level. The stable level of execution, for example, can be indicated by performance variations, such as standard deviations, between a certain number of neighboring measurement periods remaining within a certain threshold. The agent, who has been trained in the training episodes, infers the final cache management policy during the final, inferring episode.

An electronic device for recovering a database (DB) and a method of operating the electronic device are provided. The electronic device includes a non-volatile first memory configured to store a DB, a volatile second memory, and a processor operably connected to the first memory and the second memory. The processor may determine whether the DB is corrupted, may perform first integrity check of the DB after initializing a DB cache in which at least a portion of the DB is loaded to a user space of the second memory when it is determined that the DB is corrupted, may perform second integrity check of the DB after initializing an operating system (OS) cache in which at least a portion of the DB is loaded to a kernel space of the second memory when the first integrity check of the DB fails, and may perform a task on a DB file when the first integrity check or the second integrity check of the DB is successful.