Patent classifications
G06F2211/002
SYSTEMS AND METHODS FOR STORAGE PARALLELISM
One method includes streaming a data segment to a write buffer corresponding to a virtual page including at least two physical pages. Each physical page is defined within a respective solid-state storage element. The method also includes programming contents of the write buffer to the virtual page, such that a first portion of the data segment is programmed to a first one of the physical pages, and a second portion of the data segment is programmed to a second one of the physical pages.
System, Apparatus And Method For Recovering Link State During Link Training
In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.
System, Apparatus And Method For Secure Communication On A Bus
In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.
Hot plugging peripheral connected interface express (PCIe) cards
Examples provided herein relate to hot plugging PCIe cards. For example, a field programmable gate array (FPGA) communicably coupled to a PCIe bus may detect a new PCIe card physically connected to the PCIe bus. The FPGA may access configuration information stored by the FPGA that is associated with the PCIe bus. The FPGA may determine, based on the accessed configuration information, whether to facilitate connection of the new PCIe card to the PCIe bus. Responsive to determining that connection of the new PCIe card to the PCIe bus should be facilitated, the new PCIe card may be trained to communicate with the PCIe bus and an upstream device communicably coupled to the PCIe bus.
HOT PLUGGING PERIPHERAL CONNECTED INTERFACE EXPRESS (PCIe) CARDS
Examples provided herein relate to hot plugging PCIe cards. For example, a field programmable gate array (FPGA) communicably coupled to a PCIe bus may detect a new PCIe card physically connected to the PCIe bus. The FPGA may access configuration information stored by the FPGA that is associated with the PCIe bus. The FPGA may determine, based on the accessed configuration information, whether to facilitate connection of the new PCIe card to the PCIe bus. Responsive to determining that connection of the new PCIe card to the PCIe bus should be facilitated, the new PCIe card may be trained to communicate with the PCIe bus and an upstream device communicably coupled to the PCIe bus.
Systems and methods for storage space recovery
One apparatus includes a storage division selection module configured to select a storage division of a solid-state storage medium for recovery. The solid-state storage medium includes a plurality of storage divisions. Each storage division includes a plurality of storage locations. The apparatus also includes an erase module configured to erase the selected storage division. The apparatus includes a storage division recovery module configured to store a sequence indicator in the erased storage division. The sequence indicator is indicative of an ordered sequence of the plurality of storage divisions, and the sequence indicator is determined by reading information stored with data on the plurality of storage divisions.
Charging apparatus having backup function
A charging apparatus having a backup function includes a first connecting interface, a second connecting interface, a processing unit, a memory unit, and an authorizing unit. The first connecting interface is adapted to receive a power source. When the processing unit authorizes the first electronic device, the processing unit activates the backup function to back up data stored on a first electronic device connected to the second connecting interface into the memory unit. Hence, a user can use the charging apparatus to charge the first electronic device, and to back up the data stored on the first electronic device into the memory unit or to restore the data stored on the memory unit into the first electronic. The user of the first electronic device can effortlessly enjoy the data backup and restore functionality.
Apparatus and method of a concurrent data transfer of multiple regions of interest (ROI) in an SIMD processor system
This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.
Method to minimize the number of IRQ lines from peripherals to one wire
A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.
Apparatus, system, and method for a storage area network
An apparatus and system are disclosed for a storage area network (SAN). In one embodiment, a computer system includes an internal storage device and an internal storage controller. In this embodiment, the internal storage controller is configured to implement a SAN that includes at least the internal storage device and a storage device external to the computer system. In this embodiment, the internal storage controller is further configured to service a storage request received from a client that involves data stored by the internal storage device. In this embodiment, the internal storage controller is configured to communicate with the external storage device via a network.