Patent classifications
G06F2211/007
ROBOTIC CATHETER SYSTEM WITH VARIABLE DRIVE MECHANISM
A robotic catheter procedure system is provided. The robotic catheter procedure system includes a bedside system and a remote workstation. The bedside system includes a percutaneous device and a drive mechanism configured to engage and to impart an axial force to the percutaneous device and to advance and retract the percutaneous device. The bedside system includes an actuator providing torque to the drive mechanism to impart the axial force to the percutaneous device, and the torque provided by the actuator is variable. The remote workstation includes a user interface configured to receive a first user input and a control system operatively coupled to the user interface. The control system is configured to communicate a control signal to the actuator. The control signal is based upon the first user input and a second input, and the actuator provides torque to the drive mechanism in response to the control signal.
Variable data printing pipeline for digital printing
The present invention generally relates to a method for variable data printing. A data set of compressed data is provided. The data set corresponds to a basic image layout comprising a plurality of dots. Using at least one general purpose computation on graphics processing unit the compressed data is decompressed to obtain decompressed data corresponding to the basic image layout. To each dot of the plurality of dots of the basic image layout a color value is assigned based on a reference entry of a color lookup table such that a decompressed first customized image layout to be printed is obtained. The decompressed first customized image layout is provided to at least one printer device. At least the decompressed first customized image layout is printed. The at least one printer device continuously prints subsequent decompressed customized image layouts at a predefined minimum printing speed.
Efficient embedding table storage and lookup
The present disclosure provides systems, methods, and computer program products for providing efficient embedding table storage and lookup in machine-learning models. A computer-implemented method may include obtaining an embedding table comprising a plurality of embeddings respectively associated with a corresponding index of the embedding table, compressing each particular embedding of the embedding table individually allowing each respective embedding of the embedding table to be decompressed independent of any other embedding in the embedding table, packing the embedding table comprising individually compressed embeddings with a machine-learning model, receiving an input to use for locating an embedding in the embedding table, determining a lookup value based on the input to search indexes of the embedding table, locating the embedding based on searching the indexes of the embedding table for the determined lookup value, and decompressing the located embedding independent of any other embedding in the embedding table.
INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD OF INTEGRATED CIRCUIT DEVICE
An integrated circuit device includes a shuffler, a logic unit and registers each including two or more bit storages. The shuffler receives an address indicating one of the registers and data bits, selects target bit storages at which the data bits are to be stored from among bit storages of the registers depending on a shuffle configuration and the address, stores the data bits into the target bit storages, and transfers the data bits from the target bit storages depending on the shuffle configuration. The logic unit receives the data bits transferred from the shuffler and operates using the received data bits. The shuffle configuration is adjusted when a reset operation is performed.
METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR RECOGNIZING REDUCIBLE CONTENTS IN DATA TO BE WRITTEN
Techniques recognize reducible contents in data to be written. The techniques involve receiving information related to data to be written, the information indicating that the data to be written comprises reducible contents, the reducible contents comprising data with a first reduction pattern. The techniques further involve recognizing the reducible contents in the data to be written based on the information. The techniques further involve reducing the reducible contents based on the first reduction pattern. With such techniques, active I/O pattern recognition with communication between applications and storage devices may be accomplished. In addition, with such techniques, it is easy/simple to expand recognizable new patterns, and I/O pattern limitations in standard approaches no longer exist.
Memory management method, memory storage device and memory controlling circuit unit
A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: defining a first data management rule for a first type physical unit and a second data management rule for a second type physical unit, and a data density of the first type physical unit is lower than the data density of the second type physical unit; if a first physical unit belongs to the first type physical unit, managing the first physical unit according to the first data management rule to make the data stored in the first physical unit conforming to a first reliability level; and if the first physical unit belongs to the second type physical unit, managing the first physical unit according to the second data management rule to make the data stored in the first physical unit conforming to a second reliability level.
SYSTEMS AND METHODS FOR CREATING INDIVIDUALIZED PROCESSING CHIPS AND ASSEMBLIES
Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design. For each individualized processing chip the individualized processing chip design is provided for fabrication of the individualized processing chip according to the individualized processing chip design. The individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.
Scrambling apparatus and method thereof
A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.
COMBINED SECURE MAC AND DEVICE CORRECTION USING ENCRYPTED PARITY WITH MULTI-KEY DOMAINS
In one example a computer implemented method comprises generating an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits, applying a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits, generating a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits, encoding the first plurality of data blocks and the metadata block to generate a first encoded data set, and providing the encoded data set and the encoded metadata block for storage on a memory module. Other examples may be described.
Efficient Embedding Table Storage and Lookup
The present disclosure provides systems, methods, and computer program products for providing efficient embedding table storage and lookup in machine-learning models. A computer-implemented method may include obtaining an embedding table comprising a plurality of embeddings respectively associated with a corresponding index of the embedding table, compressing each particular embedding of the embedding table individually allowing each respective embedding of the embedding table to be decompressed independent of any other embedding in the embedding table, packing the embedding table comprising individually compressed embeddings with a machine-learning model, receiving an input to use for locating an embedding in the embedding table, determining a lookup value based on the input to search indexes of the embedding table, locating the embedding based on searching the indexes of the embedding table for the determined lookup value, and decompressing the located embedding independent of any other embedding in the embedding table.