In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.

In one embodiment, a processor includes a core to execute instructions, a cache memory coupled to the core, and a cache controller coupled to the cache memory. The cache controller, responsive to a first load request having a first priority level, is to insert data of the first load request into a first entry of the cache memory and set an age indicator of a metadata field of the first entry to a first age level, the first age level greater than a default age level of a cache insertion policy for load requests, and responsive to a second load request having a second priority level to insert data of the second load request into a second entry of the cache memory and to set an age indicator of a metadata field of the second entry to the default age level, the first and second load requests of a first thread. Other embodiments are described and claimed.

Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.