Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Disclosed are a method and apparatus for processing data, a medium, and a device. The method includes: determining target data to be stored at a target memory address of a target memory and a target key corresponding to the target memory address; determining a target transposition algorithm corresponding to the target data; encrypting the target data based on the target key and the target transposition algorithm, to obtain encrypted data; and storing the encrypted data at the target memory address of the target memory. With the solution, the target data to be stored are enabled to be encrypted first based on the target key and the target transposition algorithm, which therefore enables to change the target data from plaintext to ciphertext, which therefore enables to store the ciphertext at the target memory address of the target memory.

A method and device are provided in which the memory subsystem receives a range of system addresses. An address encoder of the memory subsystem encodes the system addresses to generate encoded system addresses. A first number of least significant bits (LSBs) subject to change in encoding each of the system addresses in the range is based on a lesser of a second number of trailing 0s in a binary representation of the base address and a third number of trailing 0s in a binary representation of a fourth number of the system addresses in the range. In encoding the system addresses, bit values of remaining bits in the encoded system addresses are equal to corresponding bit values in the system addresses.