Systems and methods for rules-based decisioning of events are disclosed. In one embodiment, a method may include: creating an in-memory cache by parsing stored checkpoints, signals, and rules definitions; receiving a checkpoint request; prioritizing the checkpoint request; preparing a basic context, comprising a limited set of objects, for the checkpoint request; using the in-memory cached definitions, generating at least one of a raw signal, an engineered signal, and a secondary signal for the checkpoint request based on the basic context; using the in-memory cached definitions, executing rules on at least one of the basic context, the raw signal, the engineered signal, and the secondary signal to generate a list of potential decisions; reducing the list of potential decisions to a list of final decisions; publishing the final decisions and supporting data rules and signals execution details; and executing the final decisions.

A system and method for recording video healthcare information of an individual under care based on properties of the information without deleting data, includes a device for capturing data relating to an individual, and configured to transmit a signal identifying the device, a memory for storing rules relating to the device, a buffer, a database; and a processor. The processor receives the device identification signal and said data, and retrieves the rules from the memory. Based on the rules, the processor determines, whether the data is to be stored in the database; or stored in the buffer. Based on the content of the data, the processor determines the location of the device, the time that the data was recorded, whether the individual recorded is identified as the individual under care, and the activity performed by the individual. Based on the rules, the location of the device, the recording time, the identification of the individual under care; and the activity, whether the data is to be stored in the database; or eliminated from the buffer.

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.

A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.

Implementations provide self-consistent, temporary, secure storage of information. An example system includes short-term memory storing a plurality of key records and a cache storing a plurality of data records. The key records and data records are locatable using participant identifiers. Each key record includes a nonce and each data record includes an encrypted portion. The key records are deleted periodically. The system also includes memory storing instructions that cause the system to receive query parameters that include first participant identifiers and to obtain a first nonce. The first nonce is associated with the first participant identifiers in the short-term memory. The instructions also cause the system to obtain data records associated with the first participant identifiers in the cache, to build an encryption key using the nonce and the first participant identifiers, and to decrypt the encrypted portion of the obtained data records using the encryption key.

Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.