A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.

Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color and graphics pipeline circuitry to bypass a memory access for the first virtual page based on the first page table entry in response to determination that the first virtual page is cleared to the clear color and determine a color associated with the first virtual page without performing a memory access to the first virtual page.

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with an equal preference for eviction. The cache controller provides a further selection among this plurality of candidates based upon content data read from those candidates themselves as part of the cache access operation which resulted in the cache miss leading to the cache replacement requiring the victim selection. The content data used to steer this second stage of victim selection may include transience specifying data and, for example, in the case of a cache memory comprising a translation lookaside buffer 6, page size data, type of translation data, memory type data, permission data and the like.

A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

In some embodiments, a memory overlay system comprises a translation lookaside buffer (TLB) that includes an entry that specifies a virtual address range that is a subset of a virtual address range specified by another entry. In response to an indication from the TLB that both of the entries are TLB hits for the same memory operation, a selection circuit is configured to select, based on one or more selection criteria, one of the two entries. The selection circuit may then cause the selected TLB entry including the corresponding physical address information and memory attributes to be provided to a memory interface.