Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Some embodiments modify caching server operation to evict cached content based on a deterministic and multifactor modeling of the cached content. The modeling produces eviction scores for the cached items. The eviction scores are derived from two or more factors of age, size, cost, and content type. The eviction scores determine what content is to be evicted based on the two or more factors included in the eviction score derivation. The eviction scores modify caching server eviction operation for specific traffic or content patterns. The eviction scores further modify caching server eviction operation for granular control over an item's lifetime on cache.

A storage management method includes receiving a degrade signal indicating a degraded state of a virtual disk associated with a host system. Rebuild-flush operations may be performed. The operations may include writing, to the virtual disk and also to a hot spare drive (HSP) associated with the virtual disk, valid-modified data, stored in a host storage cache, associated with the virtual disk. In contrast, valid-unmodified storage cache data associated with the virtual disk, may be written to the HSP only. After the rebuild-flush completes, the virtual disk may be rebuilt. During rebuild, however, any cached-LBA may be skipped where traditional RAID rebuild operations are performed for un-cached LBAs only.

A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

A system and method for efficiently caching metadata in a storage system. Addresses from a plurality of I/O accesses to the storage system are captured and then a frequency domain representation of the addresses is generated. The frequency domain representation is used to measure the randomness of the various applications which are accessing the storage system. Scores are generated based on the measure of randomness, and scores are assigned to the various regions of the logical address space. Scores are then assigned to the metadata pages which are stored in the cache based on the region of the logical address space to which the metadata pages correspond. The scores are used when determining which metadata pages to evict from the cache. The cache will attempt to evict those metadata pages which correspond to regions of the logical address space that are servicing random I/O accesses.

Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

An apparatus having a memory and a controller is disclosed. The memory may have a write head and sectors in tracks. The controller may have a sector map and a translation map and may be configured to (i) receive a write command having a logical block address and a range value, (ii) examine the sector map to find a sector sequence (a) marked free, (b) about to reach the write head and (c) at least as long as the range value, (iii) write new data in the sector sequence, (iv) update the translation map to associate the logical block address of the write command with a physical address of the written sectors and (v) update the sector map according to the sectors written. Each entry in the sector map generally corresponds to a respective sector and indicates whether the respective sector contains valid data or is free.

A data processing method and an acceleration unit are provided. The method includes: S11, reading a row of a target matrix as a target row; S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset, and writing each element in the shifted target row into a corresponding row buffer respectively; S13, reading a next row of the target row from the target matrix as a new target row, if the next row of the target row is not the last row of the target matrix and an available storage space exists in the row buffers; S14, reading corresponding elements from each row buffer according to a preset rule, and writing the elements read from each row buffer into an output buffer as a row, step S14 is repeated until all elements in all row buffers are written into the output buffer.

A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.

Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.