Systems and method determine a fluid efficiency of a fluid that flows through a fluid power system. Characteristics of the fluid is monitored in real-time as the fluid flows through the fluid monitoring device that is coupled to the fluid power system as the fluid flows through the fluid power system. A fluid status is determined in real-time that is associated with fluid parameters of the fluid that is determined from the fluid parameters detected by the fluid monitoring device. The fluid status of the fluid is determined in real-time when the fluid status indicates that a corrective action is to be executed to increase a quality of the fluid and an assessment of the corrective action that is to be executed is generated based on the fluid parameters. Degradation of the components of the fluid power system increases without the corrective action being executed to the fluid.

A system and method for large-scale lane marking detection using multimodal sensor data are disclosed. A particular embodiment includes: receiving image data from an image generating device mounted on a vehicle; receiving point cloud data from a distance and intensity measuring device mounted on the vehicle; fusing the image data and the point cloud data to produce a set of lane marking points in three-dimensional (3D) space that correlate to the image data and the point cloud data; and generating a lane marking map from the set of lane marking points.

A system and method for large-scale lane marking detection using multimodal sensor data are disclosed. A particular embodiment includes: receiving image data from an image generating device mounted on a vehicle; receiving point cloud data from a distance and intensity measuring device mounted on the vehicle; fusing the image data and the point cloud data to produce a set of lane marking points in three-dimensional (3D) space that correlate to the image data and the point cloud data; and generating a lane marking map from the set of lane marking points.

Transaction-enabled systems and methods for royalty apportionment and stacking are disclosed. An example system may include a plurality of royalty generating elements (a royalty stack) each related to a corresponding one or more of a plurality of intellectual property (IP) assets (an aggregate stack of IP). The system may further include a royalty apportionment wrapper to interpret IP licensing terms and apportion royalties to a plurality of owning entities corresponding to the aggregate stack of IP in response to the IP licensing terms and a smart contract wrapper. The smart contract wrapper is configured to access a distributed ledger, interpret an IP description value and IP addition request, to add an IP asset to the aggregate stack of IP, and to adjust the royalty stack.

Transaction-enabled systems and methods for royalty apportionment and stacking are disclosed. An example system may include a plurality of royalty generating elements (a royalty stack) each related to a corresponding one or more of a plurality of intellectual property (IP) assets (an aggregate stack of IP). The system may further include a royalty apportionment wrapper to interpret IP licensing terms and apportion royalties to a plurality of owning entities corresponding to the aggregate stack of IP in response to the IP licensing terms and a smart contract wrapper. The smart contract wrapper is configured to access a distributed ledger, interpret an IP description value and IP addition request, to add an IP asset to the aggregate stack of IP, and to adjust the royalty stack.

A method for generating a predictive model for quantization parameters of a neural network is described. The method comprises accessing a first vector of data values corresponding to input values to a first layer implemented in a neural network, generating a feature vector of one or more features extracted from the data values of the first vector, accessing a second vector of data values corresponding to the input values of a second layer implemented in the neural network, subsequent to the first layer, generating a target vector of data values comprising one or more quantization parameters for the second layer, from the data values of the second vector, evaluating, on the basis of the feature vector and the target vector, a predictive model for predicting the one or more quantization parameters of the second layer and modifying the predictive model on the basis of the evaluation.

An information processing device according to the present disclosure includes: an acquisition unit that acquires a model having a structure of a neural network and input information input to the model; and a generation unit that generates basis information indicating a basis for an output of the model after the input information is input to the model based on state information indicating a state of the model after the input of the input information to the model.

An information processing device according to the present disclosure includes: an acquisition unit that acquires a model having a structure of a neural network and input information input to the model; and a generation unit that generates basis information indicating a basis for an output of the model after the input information is input to the model based on state information indicating a state of the model after the input of the input information to the model.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.