A quantum system controller configured to perform (near) real-time quantum error correction is provided. The controller comprises a processing device comprising at least one first processing element; a time-indexed command (TIC) sequencer comprising at least one second processing element; and a plurality of driver controller elements configured to control the operation of respective components and associated with respective buffers and processing elements. The processing device is configured to generate commands and the TIC sequencer is configured to cause the time-indexed execution of the commands by the appropriate driver controller elements. The controlling of real-time operations of the quantum computer by the TIC sequencer enables the processing device to generate commands based on conditionals evaluated based on input data indicating quantum errors that are likely present in a quantum calculation being performed by the quantum computer such that commands addressing the quantum errors are generated and executed in (near) real-time.

A quantum system controller configured to perform (near) real-time quantum error correction is provided. The controller comprises a processing device comprising at least one first processing element; a time-indexed command (TIC) sequencer comprising at least one second processing element; and a plurality of driver controller elements configured to control the operation of respective components and associated with respective buffers and processing elements. The processing device is configured to generate commands and the TIC sequencer is configured to cause the time-indexed execution of the commands by the appropriate driver controller elements. The controlling of real-time operations of the quantum computer by the TIC sequencer enables the processing device to generate commands based on conditionals evaluated based on input data indicating quantum errors that are likely present in a quantum calculation being performed by the quantum computer such that commands addressing the quantum errors are generated and executed in (near) real-time.

A method for detecting a two-qubit correlated dephasing error includes accessing a signal of a quantum system, where the quantum system includes a plurality of qubits. Every qubit has a nonzero rate of dephasing and some qubits have a nonzero rate of correlated dephasing. The signal further includes information about a matrix that includes diagonal elements and off-diagonal elements. The off-diagonal elements of the matrix are 2 s-sparse. The method further includes performing randomized measurements of the off-diagonal elements of the matrix and recovering the matrix based on a direct measurement of the diagonal elements of the matrix.

A method for detecting a two-qubit correlated dephasing error includes accessing a signal of a quantum system, where the quantum system includes a plurality of qubits. Every qubit has a nonzero rate of dephasing and some qubits have a nonzero rate of correlated dephasing. The signal further includes information about a matrix that includes diagonal elements and off-diagonal elements. The off-diagonal elements of the matrix are 2 s-sparse. The method further includes performing randomized measurements of the off-diagonal elements of the matrix and recovering the matrix based on a direct measurement of the diagonal elements of the matrix.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Methods, systems and apparatus for benchmarking quantum computing hardware. In one aspect, a method includes defining an initial circuit configured to operate on an array of qubits, wherein the initial circuit comprises multiple instances of the two-qubit gate, wherein each instance of the two-qubit gate performs a same operation on a respective pair of neighboring qubits in the array; partitioning the initial circuit into multiple layers, wherein instances of the two-qubit gate in a respective layer can be implemented in parallel; for each of the multiple layers: constructing benchmarking circuits for the layer, wherein each benchmarking circuit for the layer comprises one or more cycles of quantum gates, each cycle comprising: the layer of instances of the two-qubit gate, and a plurality of single qubit gates; implementing the constructed benchmarking circuits to obtain experimental benchmarking data; and adjusting control parameters of the control model using the experimental benchmarking data.

Methods, systems and apparatus for benchmarking quantum computing hardware. In one aspect, a method includes defining an initial circuit configured to operate on an array of qubits, wherein the initial circuit comprises multiple instances of the two-qubit gate, wherein each instance of the two-qubit gate performs a same operation on a respective pair of neighboring qubits in the array; partitioning the initial circuit into multiple layers, wherein instances of the two-qubit gate in a respective layer can be implemented in parallel; for each of the multiple layers: constructing benchmarking circuits for the layer, wherein each benchmarking circuit for the layer comprises one or more cycles of quantum gates, each cycle comprising: the layer of instances of the two-qubit gate, and a plurality of single qubit gates; implementing the constructed benchmarking circuits to obtain experimental benchmarking data; and adjusting control parameters of the control model using the experimental benchmarking data.

Methods, systems, and apparatus for quantum data processing. In one aspect, a method includes storing, in a quantum memory, multiple copies of a quantum state, comprising, for each copy of the quantum state, i) probing, by an initialized quantum sensor, a target system to obtain an evolved quantum state of the quantum sensor, ii) transducing the evolved quantum state of the quantum sensor into a quantum state of a quantum buffer, iii) logically encoding the quantum state of the quantum buffer into a quantum error correcting code, and iv) moving the logically encoded quantum state of the quantum buffer into the quantum memory; loading the multiple copies of the quantum state in the quantum memory into a quantum computer; processing, by the quantum computer, the multiple copies of the quantum state to obtain a purified quantum state; and measuring the purified quantum state to determine properties of the target system.

Methods, systems, and apparatus for quantum data processing. In one aspect, a method includes storing, in a quantum memory, multiple copies of a quantum state, comprising, for each copy of the quantum state, i) probing, by an initialized quantum sensor, a target system to obtain an evolved quantum state of the quantum sensor, ii) transducing the evolved quantum state of the quantum sensor into a quantum state of a quantum buffer, iii) logically encoding the quantum state of the quantum buffer into a quantum error correcting code, and iv) moving the logically encoded quantum state of the quantum buffer into the quantum memory; loading the multiple copies of the quantum state in the quantum memory into a quantum computer; processing, by the quantum computer, the multiple copies of the quantum state to obtain a purified quantum state; and measuring the purified quantum state to determine properties of the target system.

A method includes, storing a set of valid codewords including: a first valid functional codeword representing a functional state of a controller subsystem; a first valid fault codeword representing a fault state of the controller subsystem and characterized by a minimum hamming distance from the first valid functional codeword; a second valid functional codeword representing a functional state of a controller; and a second valid fault codeword representing a fault state of the controller; in response to detecting functional operation of the controller subsystem, storing the first valid functional codeword in a first memory; in response to detecting a match between contents of the first memory and the first valid functional codeword, outputting the second valid functional codeword; in response to detecting a mismatch between contents of the first memory and every codeword in the first set of valid codewords, outputting the second valid fault codeword.