A method of operating a graphics processor when rendering a frame representing a view of a scene using a ray tracing process in which part of the processing for a ray tracing operation is offloaded to a texture mapper unit of the graphics processor. Thus, when the graphics processor's execution unit is executing a program to perform a ray tracing operation the execution unit is able to message the texture mapper unit to perform one or more processing operations for the ray tracing operation. This operation can be triggered by including an appropriate instruction to message the texture mapper unit within the ray tracing program.

A method of operating a graphics processor when rendering a frame representing a view of a scene using a ray tracing process in which part of the processing for a ray tracing operation is offloaded to a texture mapper unit of the graphics processor. Thus, when the graphics processor's execution unit is executing a program to perform a ray tracing operation the execution unit is able to message the texture mapper unit to perform one or more processing operations for the ray tracing operation. This operation can be triggered by including an appropriate instruction to message the texture mapper unit within the ray tracing program.

PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Techniques for rendering two-dimensional vector graphics are described. The techniques include using a central processing unit to generate tessellate triangles along a vector path in which each of the tessellate triangles is represented by a set of vertices. From the tessellate triangles, an index buffer and a compressed vertex buffer are generated. The index buffer includes a vertex index for each vertex of each of the tessellate triangles. The compressed vertex buffer includes a vertex buffer entry for each unique vertex that maps to one or more vertex indices of the index buffer. The index buffer and the compressed vertex buffer are provided to a graphics processing unit to render the vector path with anti-aliasing.

Techniques for rendering two-dimensional vector graphics are described. The techniques include using a central processing unit to generate tessellate triangles along a vector path in which each of the tessellate triangles is represented by a set of vertices. From the tessellate triangles, an index buffer and a compressed vertex buffer are generated. The index buffer includes a vertex index for each vertex of each of the tessellate triangles. The compressed vertex buffer includes a vertex buffer entry for each unique vertex that maps to one or more vertex indices of the index buffer. The index buffer and the compressed vertex buffer are provided to a graphics processing unit to render the vector path with anti-aliasing.

Data transformation caching in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers, including: identifying, in dependence upon one or more machine learning models to be executed on the GPU servers, one or more transformations to apply to a dataset; generating, in dependence upon the one or more transformations, a transformed dataset; storing, within one or more of the storage systems, the transformed dataset; receiving a plurality of requests to transmit the transformed dataset to one or more of the GPU servers; and responsive to each request, transmitting, from the one or more storage systems to the one or more GPU servers without re-performing the one or more transformations on the dataset, the transformed dataset.

Data transformation caching in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers, including: identifying, in dependence upon one or more machine learning models to be executed on the GPU servers, one or more transformations to apply to a dataset; generating, in dependence upon the one or more transformations, a transformed dataset; storing, within one or more of the storage systems, the transformed dataset; receiving a plurality of requests to transmit the transformed dataset to one or more of the GPU servers; and responsive to each request, transmitting, from the one or more storage systems to the one or more GPU servers without re-performing the one or more transformations on the dataset, the transformed dataset.

Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.