Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.

A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.

Embodiments of this application provide a rendering method and apparatus, and the like. The method includes: A processor (which is usually a CPU) modifies a rendering instruction based on a relationship between a first frame buffer and a second frame buffer, so that a GPU renders a rendering job corresponding to the first frame buffer to the second frame buffer based on a new rendering instruction. In this application, render passes of one or more frame buffers are redirected to another frame buffer. In this way, memory occupation in a rendering process of an application program is effectively reduced, bandwidth of the GPU is reduced, and power consumption can be reduced.

In a graphics processing unit (GPU), receiving an input image comprising an array of pixels. Each pixel having a grayscale value from a range of N grayscale values. For each particular input patch of pixels of a set of input patches partitioning the input image and in parallel for each particular grayscale value the range, counting the number of pixels in the particular input patch having the particular grayscale value. In parallel for each particular input patch of pixels of a set of input patches partitioning the input image, creating an output image patch as an ordered sequence of N pixels, with the color value of the nth pixel in each corresponding output patch representing the count of pixels in the particular input patch having the nth grayscale value. Combining the output image patches into a single composite output image of N pixels, the pixel value of the nth pixel in the single composite output image corresponding to the count of pixels in the input image having the nth grayscale value.

In a graphics processing unit (GPU), receiving an input image comprising an array of pixels. Each pixel having a grayscale value from a range of N grayscale values. For each particular input patch of pixels of a set of input patches partitioning the input image and in parallel for each particular grayscale value the range, counting the number of pixels in the particular input patch having the particular grayscale value. In parallel for each particular input patch of pixels of a set of input patches partitioning the input image, creating an output image patch as an ordered sequence of N pixels, with the color value of the nth pixel in each corresponding output patch representing the count of pixels in the particular input patch having the nth grayscale value. Combining the output image patches into a single composite output image of N pixels, the pixel value of the nth pixel in the single composite output image corresponding to the count of pixels in the input image having the nth grayscale value.

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Systems, devices, and techniques are generally described to transmit image data. An image file including image data may be identified. The image data may be divided into a plurality of portions. The plurality of portions may include a first portion corresponding to a first position in the image data and a second portion corresponding to a second position in the image data. The image data may be modified to produce a shuffled image. The shuffled image may indicate that the first portion corresponds to a third position and the second portion corresponds to a fourth position. The shuffled image may be sent to a recipient computing device. The recipient computing device may render the first portion at the first position and the second portion at the second position to display the image data.

Systems, devices, and techniques are generally described to transmit image data. An image file including image data may be identified. The image data may be divided into a plurality of portions. The plurality of portions may include a first portion corresponding to a first position in the image data and a second portion corresponding to a second position in the image data. The image data may be modified to produce a shuffled image. The shuffled image may indicate that the first portion corresponds to a third position and the second portion corresponds to a fourth position. The shuffled image may be sent to a recipient computing device. The recipient computing device may render the first portion at the first position and the second portion at the second position to display the image data.

Methods, apparatuses, and computer program products for overlaying multisource media in VRAM are described.