A method the following operations: downscaling an input image to generate a scaled image; performing, to the scaled image, a first convolutional neural networks (CNN) modeling process with first non-local operations, to generate global parameters; and performing, to the input image, a second CNN modeling process with second non-local operations that are performed with the global parameters, to generate an output image corresponding to the input image. A system is also disclosed herein.

An ultrasound imaging system includes a cine buffer in which image frames produced during an examination are stored. A processor is programmed to select one or more image frames from the cine buffer for presentation to an operator for approval and inclusion in a patient record or other report. The operator can accept the proposed image frames or can select one or more other image frames from the cine buffer. The processor may select image frames at spaced intervals in the cine buffer for presentation. Alternatively, the processor compares image frames in the cine buffer with one or more target image frames. Image frames that are similar to the target image frames are presented to the operator to confirm. Alternatively, image frames can be selected by the processor that contain a specific feature or that are similar to image frames that were previously selected by the operator when performing a particular type of examination.

An ultrasound imaging system includes a cine buffer in which image frames produced during an examination are stored. A processor is programmed to select one or more image frames from the cine buffer for presentation to an operator for approval and inclusion in a patient record or other report. The operator can accept the proposed image frames or can select one or more other image frames from the cine buffer. The processor may select image frames at spaced intervals in the cine buffer for presentation. Alternatively, the processor compares image frames in the cine buffer with one or more target image frames. Image frames that are similar to the target image frames are presented to the operator to confirm. Alternatively, image frames can be selected by the processor that contain a specific feature or that are similar to image frames that were previously selected by the operator when performing a particular type of examination.

A texture cache comprises at least two banks of cache storage to cache texels for processing in texture mapping operations. Access to the cached texels corresponding to a given chunk of texels of a given texture image is controlled according to a selected bank mapping selected from two or more bank mappings supported by the texture cache access control circuitry. Each bank mapping corresponds to a different mapping of the respective texels within the given chunk to the banks of cache storage. In at least one operating mode, the selected bank mapping is selected for the given chunk of texels of the given texture image depending on: at least one of first/second chunk position coordinates associated with the given chunk of texels; and at least one further texture attribute associated with the given texture image.

A texture cache comprises at least two banks of cache storage to cache texels for processing in texture mapping operations. Access to the cached texels corresponding to a given chunk of texels of a given texture image is controlled according to a selected bank mapping selected from two or more bank mappings supported by the texture cache access control circuitry. Each bank mapping corresponds to a different mapping of the respective texels within the given chunk to the banks of cache storage. In at least one operating mode, the selected bank mapping is selected for the given chunk of texels of the given texture image depending on: at least one of first/second chunk position coordinates associated with the given chunk of texels; and at least one further texture attribute associated with the given texture image.

An inspection apparatus including: a display device; and one or a plurality of processors, wherein the one or the plurality of processors is programmed to execute a method including: converting an inspection target image representing an inspection target into a virtual good article image by using a learning model, the learning model being trained so that an image representing a good article is generated based on features of a plurality of targets that are determined as good articles, generating a difference between the virtual good article image and the inspection target image as a defect candidate image, and displaying the defect candidate image on the display device.

An inspection apparatus including: a display device; and one or a plurality of processors, wherein the one or the plurality of processors is programmed to execute a method including: converting an inspection target image representing an inspection target into a virtual good article image by using a learning model, the learning model being trained so that an image representing a good article is generated based on features of a plurality of targets that are determined as good articles, generating a difference between the virtual good article image and the inspection target image as a defect candidate image, and displaying the defect candidate image on the display device.

A data transmission and protection system includes a plurality of solid-state drives (SSDs), a storage medium, a central processing unit (CPU) and a massively parallel processor (MPP). The storage medium storing an application program and a redundant array of independent disks (RAID) configuration. The CPU is coupled to the storage medium and configured to execute the application program to generate a virtual SSD interface for the plurality of SSDs according to the RAID configuration. The MPP is coupled to the virtual SSD interface and the plurality of SSDs. The MPP is configured to execute data exchange with the plurality of SSDs in response to a command received from the virtual SSD interface.

A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.