Fast and scalable architectures and methods adaptable to available resources, that (1) compute 2-D convolutions using 1-D convolutions, (2) provide fast transposition and accumulation of results for computing fast cross-correlations or 2-D convolutions, and (3) provide parallel computations using pipelined 1-D convolvers. Additionally, fast and scalable architectures and methods that compute 2-D linear convolutions using Discrete Periodic Radon Transforms (DPRTs) including the use of scalable DPRT, Fast DPRT, and fast 1-D convolutions.

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

The present disclosure provides a system and method for magnetic resonance imaging. The method may include obtaining first k-space data collected from a subject in a non-Cartesian sampling manner. The method may also include generating second k-space data by regridding the first k-space data. The method may further include generating third k-space data by calibrating the second k-space data, wherein a calibrated field of view (FOV) corresponding to the third k-space data is constituted by a central portion of an intermediate FOV corresponding to the second k-space data. The method may still further include reconstructing, using at least one of a compressed sensing algorithm or a parallel imaging algorithm, a magnetic resonance (MR) image of the subject based at least in part on the third k-space data.

One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.

Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.

One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within the 3D environment.

A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

Provided is a method for processing images. In the method, upon acquiring projection data of an object to be detected, a parsed image is acquired by performing parsing reconstruction on the projection data by calling a first image processing unit. Then a first registered image is acquired by registering the parsed image and a reference image by calling a second image processing unit, and an iterated image is acquired by performing iterative reconstruction on the projection data by calling the first image processing unit.

Examples include techniques for a fast clear of a 3-dimensional (3D) surface. Examples include re-describing 3D surface to a 2D surface using various dimension of the 3D surface as inputs in an algorithm to output a 2-dimensional (2D) surface as a re-description of the 3D surface. The algorithm to also includes additional inputs associated with a tiling mode used to read or write the 3D surface to a graphics display and a bit per pixel format to output the 2D surface. 2D surface width and height associated with the outputted 2D surface is included in a clear command to cause the 3D surface to be cleared.