The present disclosure generally relates to the field of demosaicing an image captured by an image sensor a color filter array, and more specifically relate to such a demosaicing operation using the GPU, shaders of the GPU and built-in rasterization function of the GPU.

One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

Aspects described herein are directed to leveraging multiple graphics processors, by a virtual GPU manager, to optimize the rendering of graphics in either a desktop or virtual desktop environment. The virtual GPU manager may enumerate all available physical GPUs, query performance variables including processing capacity of each of the available physical GPUs, and classify each of the physical GPUs based on the queried performance variables. Further, the virtual GPU manager may generate a logical GPU corresponding to one or more of the available physical GPUs. The virtual GPU manager may distribute graphics rendering requests across each of the plurality of available physical GPUs by way of the logical GPU.

Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

A method and apparatus for applying a two-dimensional image on a three-dimensional model composed of a polygonal mesh. The method comprises generating an adjacency structure for all triangles within the mesh, identifying a triangle within membrane containing the desired centre point, calculating spatial distances between the three vertices and desired centre checking each triangle edge to see if the distances show an intersection, if a collision is detected add the triangle to the list and iteratively processing all the triangles in the list calculate the spatial data of the single unknown vertex, check the two edges of the triangle to see if the calculated distances show an intersection, if an intersection occurs add this new triangle to the list; transforming into UV-coordinates; and applying the two-dimensional image to the three-dimensional model using the UV-coordinates.

Devices, systems, and techniques to incorporate lighting effects into computer-generated graphics. In at least one embodiment, a virtual scene comprising a plurality of lights is rendered by subdividing the virtual area and stored, in a record corresponding to a subdivision of the virtual area, information indicative of one or more lights in the virtual area selected based on a stochastic model. Pixels near a subdivision are rendered based on the light information stored in the subdivision.

Techniques for processing pixel data are provided. The techniques include, in a first mode in which blending is enabled, reading in render target color data from a memory system; blending the render target color data with one or more fragments received from a pixel shader stage to generate blended color data; outputting the blended color data to the memory system utilizing a first amount of bandwidth; in a second mode in which blending is disabled and variable rate shading is enabled, amplifying shaded coarse fragments received from the pixel shader stage to generate fine fragments; and outputting the fine fragments to the memory system utilizing a second amount of bandwidth that is higher than the first amount of bandwidth.

Techniques are disclosed relating to using cost estimates for portions of a graphics frame to schedule graphics rendering tasks. In some embodiments, a processor generates a first set of cost estimates for respective different portions of a frame for a first render and a second set of cost estimates for respective different portions of a frame for a second render. In some embodiments, the processor compares the first set of cost estimates with the second set of cost estimates. In response to an output of the comparison meeting a first threshold level of similarity, the graphics processor may use one or more portions of the frame generated by the first render for the second render instead of performing the second render for the one or more portions.

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.