A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.

A content display control apparatus includes an animation rule definition storage unit configured to store animation rule definitions. The content display control apparatus is configured to arbitrate animations based on the animation rule definitions stored in the animation rule definition storage unit in response to receiving a screen transition arbitration result and an animation execution state, and to execute the animations according to the screen transition arbitration result and an animation arbitration result.

Described are various embodiments of a digital display device for use by a user having reduced visual acuity. In one embodiment, the device comprises: a digital display medium comprising an array of pixels and operable to render a pixelated image accordingly; a light field shaping layer defined by an array of light field shaping elements and disposed relative to said digital display so to align each of said light field shaping elements with a corresponding set of said pixels to shape a light field emanating therefrom and thereby at least partially govern a projection thereof from said display medium toward the user; and a hardware processor operable on pixel data for the image such that said processed image is rendered to at least partially compensate for the user's reduced visual acuity.

Disclosed herein are system, method, and computer program product embodiments for modifying graphics rendering by transcoding a serialized command stream. An embodiment operates by receiving a command configured to instruct an API to render a graphics element. The embodiment further operates by generating, based on the command, a transcoded command configured to instruct the API to render a modified graphics element by applying a set of modification factors to a portion of the command. Subsequently, the embodiment operates by transmitting the transcoded command to the API.

The invention comprises a system of client-server visualization with hybrid data processing, having a server digital data processor, that allows for server side rendering and processing image data, and client digital data processors simultaneously connected to the server, which receives messages from the clients, creates rendered images of data sets or other data processing results and sends those rendered images and results to the clients for display or further processing. Performing certain image rendering operations on either the server or the client according to which is better suited for the tasks requested by the user at any point in time, and possibly adjusting this division of work dynamically, improves rendering speed and application responsiveness on the clients.

A method comprises monitoring a drawing time of a first frame of image, obtaining a current state of a system on chip (SOC) when the drawing time exceeds a first drawing duration, where the current state comprises a current temperature of the SOC and/or a current load of the SOC, determining whether the current state exceeds a first preset threshold, when the current state does not exceed the first preset threshold, increasing an operating frequency of the SOC in a time range, and restoring the operating frequency after the increasing of the operating frequency ends, obtaining actual drawing duration of the first frame of the image when drawing of the first frame of the image is completed, and monitoring a drawing time of a second frame of the image when the actual drawing duration does not exceed second drawing duration.

An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Systems and methods are configured to adjust the timing of rendered frame scanout in response to fluctuations in a variable frame rate at which source frames are rendered.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.