A display device is provided and includes scanning and signal lines; switch electrically coupled to scanning and signal lines; pixel electrode electrically coupled to switch and opposed to drive electrode; first and second display periods, and detection period between first and second display periods, wherein during first and second display periods, common voltage is applied to drive electrode, scanning signal is applied to scanning line and switch, pixel signal is applied to pixel electrode through signal line and switch, during detection period, AC drive signal or pulse drive signal is applied to drive electrode, and scanning signal is not applied to scanning line.

A display device is provided and includes scanning and signal lines; switch electrically coupled to scanning and signal lines; pixel electrode electrically coupled to switch and opposed to drive electrode; first and second display periods, and detection period between first and second display periods, wherein during first and second display periods, common voltage is applied to drive electrode, scanning signal is applied to scanning line and switch, pixel signal is applied to pixel electrode through signal line and switch, during detection period, AC drive signal or pulse drive signal is applied to drive electrode, and scanning signal is not applied to scanning line.

An electronic device according to various embodiments may comprise: a display; a processor; a memory; and a display drive circuit for driving the display panel, wherein the display drive circuit is configured to: receive first frame data including at least a part of a second content from the processor while a first content is displayed using the display panel; keep from storing the received first frame data in the memory at least temporarily for a designated period of time; receive second frame data including at least a part of the second content from the processor after the designated period of time; store the received second frame data in the memory; and display the second content on the display panel according to the second frame data.

The present disclosure relates to a signal processing device and an image display apparatus including the same. The signal processing device includes: an input interface to receive an image signal; a first image processor to generate first image frame data based on the image signal; a second image processor including a scaler to generate second image frame data scaled down in comparison with the first image frame data; and an output interface to output the first image frame data and the second image frame data, wherein the scaler generates at least one super pixel or super block and outputs the scaled down second image frame data including the super pixel or the super block. Accordingly, it is possible to generate the scaled down second image frame data with reduced error as compared to the first image frame data.

The signal processing device according to an embodiment of the present disclosure includes: a frame buffer to store an input image and output an output image, an output synchronization signal calculator to calculate an output synchronization signal based on an input synchronization signal and a size or a position of the output image in comparison with the input image, and an output synchronization signal output interface to output a variable output synchronization signal of which a start timing changes based on a signal from the output synchronization signal calculator, wherein a difference between a start timing of the input synchronization signal and a start timing of the output synchronization signal changes based on the size of the output image. Accordingly, a delay time may be reduced in response to the output image having a size different from a size of the input image being output.

A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.

A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.

This disclosure relates to techniques for a driving apparatus including a reordering circuit and a source driving circuit. The reordering circuit can be configured to reorder a plurality of sub-pixel data of an input data string to generate a reordered data string so as to reduce a color switching number associated with a target data line. The source driving circuit can be coupled to the reordering circuit to receive the reordered data string. The source driving circuit can be configured to drive the target data line of a display panel according to the reordered data string.

This disclosure relates to techniques for a driving apparatus including a reordering circuit and a source driving circuit. The reordering circuit can be configured to reorder a plurality of sub-pixel data of an input data string to generate a reordered data string so as to reduce a color switching number associated with a target data line. The source driving circuit can be coupled to the reordering circuit to receive the reordered data string. The source driving circuit can be configured to drive the target data line of a display panel according to the reordered data string.

Aspects of the present disclosure can receive a hardware Vsync signal from a display, generate a hardware timestamp signal based on the hardware Vsync signal, determine an error for a pulse in the hardware timestamp signal, determine whether the error for the pulse is over a threshold, synchronize a software Vsync signal based on the hardware timestamp signal, wherein the pulse of the hardware timestamp signal is ignored in synchronization based on whether the error is above the threshold, and control rendering and transmission of a frame to the display based on the synchronized software Vsync signal.