A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.

A flip-flop circuit is provided. A driver circuit is provided. The flip-flop circuit includes first to fifth input terminals and first to third output terminals, the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulation signal, and the fifth input terminal is supplied with a second pulse width modulation signal. The first output terminal supplies a first selection signal in response to the first pulse width modulation signal in a period from supply of the first trigger signal to supply of the second trigger signal, the first output terminal supplies the first selection signal in a period during which the batch selection signal is supplied, the second output terminal supplies a second selection signal in response to the second pulse width modulation signal in the period from the supply of the first trigger signal to the supply of the second trigger signal, and the third output terminal supplies a third trigger signal.

A display panel includes a plurality of pixels arranged in a matrix, the plurality of pixels respectively including a plurality of sub pixels. The plurality of sub pixels respectively includes a light emitting element, and a PWM pixel circuit configured to control a light emitting duration of the light emitting element, based on a pulse width modulation (PWM) data voltage and a sweep voltage. A plurality of PWM pixel circuits included in the display panel are driven, for each of row lines of the plurality of pixels, in an order of a data setting period for setting the PWM data voltage and then a light emitting period in which the light emitting element emits light during a duration corresponding to the set PWM data voltage according to a change of the sweep voltage.

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.

A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the second signal, and a period during which the first signal is at the high-level potential and a period during which the second signal is at the high-level potential do not overlap each other.

A display device includes a plurality of pixels. One of the pixels includes a light emitting diode and a driving circuit coupled to the light emitting diode. A display frame period includes at least two emission periods. The light emitting diode emits light according to a data signal including a gray level in each of the at least two emission periods.

A display device includes: a display unit including pixels, wherein each of the pixels includes stacks connected in series and each of the stacks includes a light emitting element; a storage to store pieces of stack number information, wherein each of the pieces of the stack number information indicates the number of stacks constituting an effective light source from among the stacks for each of the pixels; a compensator to generate compensated data by compensating image data based on the pieces of the stack number information; and a data driver to generate data voltages based on the compensated data and to provide the data voltages to the display unit. The pixels are to emit light with luminances corresponding to the data voltages.

An afterimage compensation device includes: an afterimage area detector to receive an input image, and detect an afterimage area including an afterimage in the input image; an afterimage area corrector to detect a false detection area, and generate a corrected afterimage area, the false detection area being a part of a general area that is not detected as the afterimage area and surrounded in a plurality of directions by the detected afterimage area; and a compensation data generator to adjust a luminance of the corrected afterimage area to generate compensation data.

An apparatus for driving an electro-optic display may comprise a first switch designed to supply a voltage to the electro-optic display during a first driving phase, a second switch designed to control the voltage during a second driving phase and a resistor coupled to the first and second switches for controlling the rate of decay of the voltage during the second driving phase.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.