The present application discloses a clock signal test circuit, a control method thereof, a display panel and a test device. The clock signal test circuit comprises: N clock control signal lines; M control sub-circuits, each of which includes at least two control branches, wherein each of the control branches is configured to output a signal input from the input signal line to the corresponding output signal line under the control of a signal input from the corresponding clock control signal line; and a pull-down sub-circuit including N pull-down branches, wherein each of the pull-down branches is configured to output the first power supply voltage to the corresponding output signal line under the control of the signal input from the corresponding clock control signal line.

A display device according to present disclosure comprising: a first display panel that displays a first image; a second display panel disposed on a back surface side of the first display panel to display a second image; and an image processor that acquires input image data and generates first image data corresponding to the first image and second image data corresponding to the second image based on the input image data, wherein the image processor includes a first filter circuit that performs first low-pass filter processing on the input image data, and the first filter circuit reduces a degree of the first low-pass filter processing when input gradation of the input image data is less than first gradation as compared with a case that the input gradation is greater than or equal to the first gradation.

Provided are a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an input circuit, configured to be coupled to an input signal end and a second clock signal end, respectively; a first transistor, where the first electrode of the first transistor is coupled to the output end of the input circuit, and the first transistor is a double-gate type transistor; the first gate of the first transistor is configured to be coupled to a first reference signal end, and the second gate of the first transistor is configured to be coupled to a first threshold control signal end; and an output circuit, configured to be coupled to a first clock signal end and a signal output end, respectively, where the control end of the output circuit is coupled to the second electrode of the first transistor.

A scan driving circuit, a driving method, and a display device is provided. The scan driving circuit includes a first scan unit, a first scan line, a first control circuit, and a first switching circuit. The first scan unit includes a first output terminal configured to output a first scan signal. The first control circuit is connected to the first switching circuit, and the first control circuit is configured to control turn-on or turn-off of the first switching circuit under control of the first control signal. The first scan line is connected to the first output terminal through the first switching circuit, so that the first output terminal is electrically connected to the first scan line when the first switching circuit is turned on.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

The disclosure provides a display device driving method and a display device. In driving the display device in which any one of a first frequency drive and a second frequency drive can be selected as a specific frequency, for a scanning period at the specific frequency from a start of a quenching period for a first row forming a frame to an end of a quenching period for a last row forming the frame, the scanning period in the second frequency drive is shorter than the scanning period in the first frequency drive.

The present invention provides a method of driving a display panel and a driving device. The present invention determines sub-pixels shared by sub-pixel rendering technology through comparing differences of the color components, and the sub-pixels shared by the display image are not fixed. Since the sub-pixels with the smallest absolute value of the color component difference are selected for sharing, a contrast of an edge region of an image is improved, and distortion of an edge region of an image is reduced.

The present invention provides a source driver for driving a light emitting diode panel. The source driver includes a buffer including an output terminal; and a plurality of driving circuits coupled to the buffer. Each of the plurality of driving circuits includes a constant current transistor including a gate controlled by a node voltage of the output terminal of the buffer; and a compensation unit for compensating the node voltage of the output terminal of the buffer.

Active control of light emitting diodes (LEDs) and LED packages within LED displays is disclosed. LED packages are disclosed that include a plurality of LED chips that form at least one LED pixel for an LED display or an LED panel. Each LED package may include an active electrical element that is configured to receive a control signal and actively maintain an operating state, such as brightness or grey level while other LED packages are being addressed. Active electrical elements are disclosed that are configured to provide both forward and reverse bias states to LEDs to detect adverse operating conditions including reverse leakage and deviations to forward voltage levels. LED packages are also disclosed that may self-configure based on the manner in which various input or output lines are connected.

Techniques to provide uniform luminance across a computing device display, such as an active matrix organic light emitting diode (AMOLED) display. In some examples, a computing device display may include a hole within the active area of the display that may be used for a camera, a button or some other function. The hole may result in a non-uniform voltage drop in a power supply mesh in regions of the active area near the hole. The power supply mesh may provide electrical energy to elements of the display. The techniques of this disclosure include portions of the power supply mesh that are not connected to the voltage supply bus to ensure a uniform voltage drop across the active area of the display.