A light-emitting panel and a display device are provided. The light-emitting panel includes a plurality of light-emitting components arranged in an array, a plurality of signal calculation modules, and a reference-signal generation module. A light-emitting component includes a light-emitting module and a first switch module. The light-emitting module and the first switch module are connected in series between a first power terminal and a second power terminal. A control terminal of the first switch module is connected to a signal calculation module, and the signal calculation module is connected to the reference-signal generation module. The reference-signal generation module is configured to generate a reference signal. The signal calculation module is configured to receive an original data signal and the reference signal, and generate a first data signal. The signal calculation module is further configured to generate a pulse width modulation signal, and to control the light-emitting module to emit light.

A sub-pixel for an LED display, the sub-pixel comprising a first light emitting device having a first emission beam angle and a second light emitting device having a second beam angle, the second emission beam angle being different to the first emission beam angle. There is also described a display using a plurality of the sub-pixels.

The present disclosure relates to display devices, and more specifically, to a display device with a sensor circuit capable of sensing the presence or absence of an abnormality in a signal line located in a bending area. Through these, a display device is provided that enables an accurate check to be performed for the presence or absence of an abnormality, such as a crack, or the like in signal lines located in the bending area, and thus, has a normal bending structure without defects.

According to one embodiment, a display device includes a display region where pixels are arranged. Each of the pixels includes a pixel electrode, a light emitting element, a drive transistor, a first capacitance electrode layer opposed to the pixel electrode and held at a constant potential, and an insulating layer forming an auxiliary capacitance together with the pixel electrode and the first capacitance electrode layer. A value of the auxiliary capacitance of the first pixel, of the values of the auxiliary capacitance of the pixels is the largest.

A flat-panel display comprises a display substrate, an array of pixels distributed in rows and columns over the display substrate, the array having a column-control side, and column controller disposed on the column-control side of the array providing column data to the array of pixels through column-data lines. In some embodiments, rows of pixels in the array of pixels form row groups and each column of pixels in a row group receives column data through a separate column-data line. In some embodiments, each pixel in each column of pixels in the array of pixels is serially connected and each pixel in the array of pixels comprises a token-passing circuit for passing a token through the serially connected column of pixels.

Provided are a display panel and display device. The display panel includes a driver circuit, where the driver circuit includes an N-stage cascaded shift register which includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to control a signal of a second node. The third control unit is configured to receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node. The fourth control unit is connected to the third node.

A pixel array includes pixel sets adjacent to each other. A pixel set includes two pixels. Each pixel includes three sub-pixels having a quadrilateral shape. Two adjacent edges of any one of the sub-pixels adjoin the other two sub-pixels, respectively, so that each pixel has a hexagonal shape. Sub-pixels of the pixel have different colors. After a rotation by 180 degrees, shapes of three sub-pixels of one pixel in a pixel set are substantially the same as shapes of three sub-pixels of the other pixel in the pixel set, and adjacent two sub-pixels of two pixels correspond to each other.

A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

A self-compensating circuit for controlling pixels in a display includes a plurality of light-emitter circuits. Each light-emitter circuit includes a light emitter, a drive transistor, and a compensation circuit. The compensation circuit is connected to the light emitter of one or more different light-emitter circuits.

Subject matter disclosed herein relates to driving schemes that provide for improved data writing to pixels of electrowetting display devices. Subframes are defined within an input frame for providing data to pixels of an electrowetting display. Blocks of rows of pixels are also defined. The blocks are defined based upon driving schemes for the electrowetting display. In an embodiment, the driving schemes include a block driving scheme and an interlaced driving scheme. With a block driving scheme, the rows of pixels are grouped sequentially into blocks, i.e. block 1 includes rows 1-4, block 2 includes rows 5-8, etc. With an interlaced driving scheme, every Nth row is included in a block such that block 1 includes rows 1, 5, . . . , block 2 includes rows 2, 6, . . . , etc. Individual blocks are written to during the subframes thereby allowing for all rows to be handled during the input frame.