A display substrate and a display device are provided. The display substrate includes: a base substrate, including a display region; a plurality of pixel units, located in the display region, each of the plurality of pixel units including a pixel circuit structure and a light-emitting element, the light-emitting element including a first electrode, the first electrode being located at a side of the pixel circuit structure away from the base substrate, the plurality of pixel units including a first pixel unit and a second pixel unit that are adjacent to each other in a first direction; a first initialization signal line, extending in the first direction; a light-emitting control signal line, extending in the first direction; a first power line, extending in a second direction, the second direction intersecting with the first direction; a first data line, extending in the second direction, the first data line being connected with the pixel circuit structure of the first pixel unit; a second data line, extending in the second direction, the second data line being connected with the pixel circuit structure of the second pixel unit, the first data line and the second data line being arranged at two sides of the first power line, respectively; and a light transmission hole, an orthographic projection of the light transmission hole on the base substrate being not overlapped with an orthographic projection of the first electrode on the base substrate; the light transmission hole is located in a region enclosed by the first initialization signal line, the light-emitting control signal line, the first power line, and the second data line.

This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an N.sup.th frame of display data within a preset time. The processing unit receives the N.sup.th frame of display data in the (N+1).sup.th frame, and controls, based on the N.sup.th frame of display data, the display to display an N.sup.th frame of image.

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and a data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

A pixel driving circuit includes a reset sub-circuit, a compensation sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The reset sub-circuit is configured to transmit an initialization signal received from an initialization signal terminal to the light-emitting control sub-circuit. The fight-emitting control sub-circuit is configured to transmit the initialization signal to the first node. The compensation sub-circuit is configured to transmit the initialization signal from the first node to a second node so as to reset a voltage of the second node. The driving sub-circuit is configured to open a conductive path from a first voltage signal terminal to the initialization signal terminal during a process of resetting the voltage of the second node.

A display device includes: a display panel including a display area including pixels and a non-display area including a dummy pixel; a scan driver which supplies a scan signal to the display panel; a data driver which supplies a data signal to the display panel; and a timing controller which supplies a first control signal for controlling the scan driver and a second control signal for controlling the data driver. The dummy pixel is connected to a bad pixel among the pixels in the display area through a repair line, and a connection of the dummy pixel to the repair line is cut off in an initialization phase in which a voltage of an initialization power source is supplied.

A display device includes a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a semi-off switching circuit configured to control the image control signal so that the image data is cut off from the host system during a semi-off period of a predetermined time from a time when an off monitoring signal is transmitted from the host system in response to the power off signal.

A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.

This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.