An electronic device includes a first display unit, a communication unit configured to communicate with an external device including a second display unit, and a control unit configured to rotate an image to be displayed on the first display unit, in accordance with a rotational angle in a plane parallel to a screen of the first display unit, and rotate an image to be output to the external device, in accordance with the rotational angle of the first display unit and a rotational angle in a plane parallel to a screen of the second display unit.

In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.

An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.

A display device capable of performing image processing is provided. A memory node is provided in each pixel included in the display device. An intended correction data is held in the memory node. The correction data is calculated by an external device and written into each pixel. The correction data is added to image data by capacitive coupling, and the resulting data is supplied to a display element. Thus, the display element can display a corrected image. The correction enables image upconversion, for example.

A method of driving a display panel includes dividing an input image into a plurality of segments, generating a flicker value of a segment of the plurality of segments, determining whether to compensate the flicker value of the segment or not according to a segment size, compensating the flicker value of the segment based on the segment size, determining a frame rate of the display panel based on the flicker value of the segment and outputting a data voltage to the display panel in the frame rate. The flicker value of the segment is compensated based on the flicker value of the segment and flicker values of segments that are adjacent to the segment.

An image processing device includes a blender and a display quality enhancer. The blender is configured to receive a plurality of layer data, generate first image data by blending the plurality of layer data, the first image data including a plurality of pixel values corresponding to a screen in a display device, and generate pixel map data including a plurality of pixel identifications (IDs) based on the plurality of layer data, the plurality of layer data representing a plurality of images to be displayed on the screen, the plurality of pixel IDs indicating display quality enhancement algorithms to be applied to the plurality of pixel values. The display quality enhancer is configured to generate second image data including a plurality of display quality enhancement pixel values by applying the display quality enhancement algorithms to the plurality of pixel values based on the first image data and the pixel map data.

A screen includes a screen pixel array, row and column lines, a display driver integrated circuit (DDIC) circuit, a gate driver on array (GOA) circuit, a switch circuit, and an enabling signal circuit. The DDIC circuit is disposed on a side of a screen of the electronic device, and includes output channels. Each output channel is connected to two switches, each switch is connected to one row line, the GOA circuit is connected to a column line, the enabling signal circuit is connected to the switch circuit, and the screen pixel array is connected to the row and column line. The enabling signal circuit generates an enabling signal for the switch circuit. The DDIC circuit sends to-be-displayed data to the switch circuit. The switch circuit controls the two switches to alternately operate. The GOA circuit strobes a column of pixels in the screen pixel array which displays the to-be-displayed data.

A display device includes a plurality of pixel circuits each including: a light-emitting element; a pulse width modulation (PWM) controller configured to control whether to supply current to the light-emitting element; and a constant current controller configured to supply the current to the light-emitting element, wherein the constant current controller, the PWM controller, and the light-emitting element are connected in series between a first power line and a second power line to supply the current to the light-emitting element; and a transistor configured to turn off the light-emitting element during a constant current setting period is provided between the first power line and the constant current controller.

A display device including: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of data lines extending in a first direction in the display area; a fan-out unit arranged in the peripheral area and connected to the plurality of data lines; a first signal line arranged in the peripheral area; and a common power supply line arranged in the peripheral area and overlapping the fan-out unit.