The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.

A display apparatus includes a display panel including a gate line and a data line, a controller generating a source output enable signal determining an output timing of a data voltage output to the data line, and a data driver including a signal changer, generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage for each gate line by using the final source output enable signal.

A display device includes a display panel including a plurality of sensing lines and a plurality of pixels each connected to a corresponding sensing line among the plurality of sensing lines, a sensor that senses characteristic information of the plurality of pixels through the plurality of sensing lines and converts the characteristic information into sensing data having a digital format, and a compensator that converts first data received from outside of the display device into second data based on the sensing data, wherein the sensor senses characteristic information of pixels arranged in a partial area of the display panel during a transition period of a sensing period and processes sensed characteristic information as dummy data.

A display system includes a first memory and a display driver. The display system is configured to control the first memory to receive compensation information from the first memory with a first frequency and generate data signals for image data to be displayed on a display panel. The generation of the data signals comprises performing a compensation for the data signals based on the compensation information received from the first memory. The display driver is further configured to update pixels of the display panel with the data signals during an active display state. The display driver is further configured to generate updated compensation information based at least in part on the image data and the compensation information received from the first memory and transmit the updated compensation information to the first memory during the active display state with a second frequency lower than the first frequency.

An electro-optical device includes a scanning line, a data line intersecting with each other, a pixel circuit which is provided corresponding to the intersection thereof, and a wire. The pixel circuit includes a light emitting element, one transistor which controls a current flowing to the light emitting element, and the other transistor of which conduction state is controlled according to a scanning signal which is supplied to the scanning line between a gate node of the one transistor and the data line. The wire is provided between the data line and the one transistor.

The present disclosure provides a display panel and a display device. The display panel includes source driver chips. The source driver chips include charging compensation modules, and each of the charging compensation modules includes: a plurality of shift registers cascadely connected and configured to time-divisionally output a plurality of pulse signals, and a plurality of level shift circuits time-divisionally conducted in response to the plurality of the pulse signals to prevent the plurality of the level shift circuits in the source driver chips from outputting and generating a plurality electron currents at a same time, which would result in a superposition of current peaks and cause electromagnetic interference problems.

Disclosed herein is a data interface device of a display apparatus including a timing controller, encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded data transfer packet to a transfer line, and a source integrated circuit generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock, wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.

A display apparatus includes a display panel including a first surface including first pixels and a second surface including second pixels, the first surface contacting the second surface at a panel center thereof, a first source integrated circuit (IC) sequentially latching first image data, which is to be applied to the first surface, in a first direction facing the panel center at a panel edge of the first surface, and a second source IC sequentially latching second image data, which is to be applied to the second surface, in a second direction facing the panel center at a panel edge of the second surface, wherein the first direction is opposite to the second direction.

The present embodiment provides a technology for sensing a common mode voltage in the positive line and negative line of a transmission line for image data and determining whether noise occurs in the image data transmitted through the transmission line by comparing the common mode voltage with a set reference voltage.

A display device including: a sensor part including sensors; a sensor driver that transmits a sensing signal to p sensors of a first area of the sensor part in a first mode and a sensing signal to q sensors in the first area in a second mode; and a display driver that transmits a light emitting signal to pixels for the pixels to have s non-light emitting periods during one frame period in the first mode, and the light emitting signal to the pixels for the pixels have t non-light emitting periods during the one frame period in the second mode, wherein p is an integer larger than 0, q is an integer larger than p, s and t are integers larger than 1, and a sum of lengths of the t non-light emitting periods is larger than a sum of lengths of the s non-light emitting periods.