A display device includes a display panel in which a plurality of subpixels including a light emitting element that emits light by a high potential voltage supplied to a driving voltage line, and a plurality of reference voltage lines connected to the plurality of subpixels to detect a characteristic value are disposed; a data driving circuit configured to supply a low potential voltage to the driving voltage line through the plurality of reference voltage lines; a base voltage switching circuit configured to control a ground voltage node connected to a cathode electrode of the light emitting element; a current detecting circuit configured to detect a current flowing between the base voltage node and a ground; and a timing controller configured to control the base voltage switching circuit and generate a defect detection signal for the driving voltage line according to a current detected by the current detecting circuit.

Discussed is a display apparatus including a substrate including a display portion, a plurality of pixels connected to a gate line and a data line disposed in the display portion, and a gate driving circuit disposed in the display portion to drive the gate line. The gate driving circuit includes a stage circuit unit including a plurality of stage circuits respectively disposed in a plurality of division regions defined in the display portion, and a circuit repair portion configured to repair at least one of the plurality of stage circuits and including a plurality of repair patterns. Further, at least one of the plurality of repair patterns is configured to be electrically disconnected from the at least one of the plurality of stage circuits.

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection teiiuinals The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Disclosed are an array substrate, a display panel and a driving method thereof. As the control unit is provided between the first electrode and the test circuit, when the panel is subsequently tested, the control unit may provide the circuit control signal received by the first electrode to the test circuit under the control of the third electrode, so as to detect whether the panel is qualified by using the test circuit. During subsequent display, the control unit may be used to cut off the first electrode from the test circuit, and fundamentally cut off the connection between the first electrode, and the test circuit and a flexible printed circuit, so that a display abnormality does not occur even if the first electrode is short-circuited.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.

A pixel includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a first initialization transistor coupled between the first node and a first initialization voltage line, and including a gate electrode coupled to a scan line, where the first initialization voltage line is configured to supply a first initialization voltage; a first emission control transistor coupled between a fourth node and a fifth node and including a gate electrode coupled to the first node; a second emission control transistor coupled between the third node and the fifth node and including a gate electrode coupled to an emission control line; and a light-emitting element coupled between the fourth node and a driving low voltage line. The driving transistor and the first emission control transistor are different types of transistors.

A display apparatus includes: a first power line, a second power line, an IC region, a printed circuit board region, and a display panel. The IC region includes a logic block receiving a first power voltage from the first power line, an analog block receiving a second power voltage from the second power line, a first IC ground connected to the logic block, and a second IC ground connected to the analog block. The printed circuit board region includes a printed circuit board ground connected to the first IC ground and the second IC ground, a transient voltage suppressor diode including a first electrode connected to the second power line and a second electrode connected to the printed circuit board ground, and a board switch performing a switching operation between the printed circuit board ground and the first IC ground. The display panel is connected to the IC region.

A pixel includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a first initialization transistor coupled between the first node and a first initialization voltage line, and including a gate electrode coupled to a scan line, where the first initialization voltage line is configured to supply a first initialization voltage; a first emission control transistor coupled between a fourth node and a fifth node and including a gate electrode coupled to the first node; a second emission control transistor coupled between the third node and the fifth node and including a gate electrode coupled to an emission control line; and a light-emitting element coupled between the fourth node and a driving low voltage line. The driving transistor and the first emission control transistor are different types of transistors.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit may include a scan driver circuit and a scan inverter circuit. An enable transistor may be interposed between the scan driver circuit and the scan inverter circuit and may be selectively disabled to decouple the scan inverter circuit from the scan driver circuit to allow the scan inverter circuit to operate independent from the scan driver circuit. The scan inverter circuit may include a transistor that receives a scan pulse signal from the scan driver circuit and may further include additional transistors connected in a negative feedback configuration to reduce a drain-to-source voltage across the transistor to reduce leakage across the transistor during blanking times.