Patent classifications
G09G2360/06
SUB-FRAME SCANOUT FOR LATENCY REDUCTION IN VIRTUAL REALITY APPLICATIONS
A system, computer readable medium, and method for sub-frame scan-out are disclosed. The method includes the steps of dividing a frame into a plurality of slices. For each slice in the plurality of slices, the steps further include sampling a sensor associated with a head mounted display to generate sample data corresponding to the slice; adjusting one or more parameters associated with rendering operations for the slice based on the sample data; and rendering primitive data associated with a model according to the rendering operations to generate image data for the slice. Each slice is a portion of the frame and corresponds to different sample data from the sensor. Thus, adjusting of the parameters is different for each slice of the frame.
PERIPHERAL COMPONENT
Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.
ELECTRONIC APPARATUS
An apparatus includes a display device, a switch assembly configured to switch a signal source of a display signal for the display device, a processor connected to the switch assembly and configured to provide signal to the display device through the switch assembly in a first mode, and a controller connected to the switch assembly and configured to provide the display signal to the display device through the switch assembly in a second mode.
Multi-user/multi-GPU render server apparatus and methods
The invention provides, in some aspects, a system for rendering images, the system having one or more client digital data processors and a server digital data processor in communications coupling with the one or more client digital data processors, the server digital data processor having one or more graphics processing units. The system additionally comprises a render server module executing on the server digital data processor and in communications coupling with the graphics processing units, where the render server module issues a command in response to a request from a first client digital data processor. The graphics processing units on the server digital data processor simultaneously process image data in response to interleaved commands from (i) the render server module on behalf of the first client digital data processor, and (ii) one or more requests from (a) the render server module on behalf of any of the other client digital data processors, and (b) other functionality on the server digital data processor.
Program, display apparatus, television receiver, display method, and display system
A television receiver segments a part of an image depending on image information received from a communication device and pixel information representing the number of pixels in a longitudinal direction and a lateral direction of the image. The television receiver judges a size between the number of pixels in the longitudinal direction and that in the lateral direction in the pixel information, and when it is judged that the number of pixels in the longitudinal direction is larger than that in the lateral direction, displays two screens in which the segmented image and another image are juxtaposed on a display unit. Meanwhile, when it is judged that the number of pixels in the longitudinal direction is not larger than that in the lateral direction, the television receiver receives a signal designating the number of screens to be displayed on the display unit and displays the two screens in which the segmented image and another image are juxtaposed or one screen of the segmented image on the display unit depending on the received signal.
DISPLAY MODE SETTING DETERMINATIONS
Examples for generating a common video signal for an integrated GPU and the graphical processing device, based on a common display mode setting, are described. In an example, a common display mode setting is determined based on a first set of display mode settings supported by the integrated GPU and a second set of display mode settings supported by the graphical processing device. Based on the common display mode setting, video signals for the integrated GPU and the graphical processing device are generated.
ELECTRONIC DEVICE CAPABLE OF APPROPRIATELY USING VARIOUS TIME DISPLAYS
A smart watch includes a main CPU, a sub CPU, a first display unit, and a second display unit. While the main CPU and the sub CPU cooperate with each other and perform a display operation including a time display, time display processing is performed to at least either of the first display unit or the second display unit according to an operation state.
Reducing the number of scaling engines used in a display controller to display a plurality of images on a screen
Methods and apparatuses to reduce the number of scaling engines used in a display controller that displays image content associated with a plurality of image sources on a screen are provided. A first multiplexer may receive image content from a plurality of storage devices, and select first image content from one of the plurality of image sources. A first scaling engine may process the selected first image content, wherein a plurality of multiplexers can receives an output of the first scaling engine and the image content from the plurality of storage devices, respectively. Each one of the plurality of multiplexers may output either the image content input to the multiplexer or the output of the first scaling engine depending on which image content was scaled by the first scaling engine. Additionally, a plurality of post-processors may perform additional post-processing on the output of the plurality of multiplexer, respectively.
Hierarchical display-server system and method
A computing system includes a hierarchical set of servers. The hierarchical set includes a master server and one or more slave server. The master server and slave servers communicate with at least one non-intelligent user system over a communications network. The master server has full access to each non-intelligent user system. The master server controls access permissions for each slave server to the non-intelligent user system(s). Each higher level slave server can control access permissions for sub-level slave server(s) to the non-intelligent user system(s). A master or, if permitted access, a slave server, creates a window in a display of the non-intelligent user system, and can provide access to the window to any lower-level slave server to send pixels to fill that window. The pixels can be the graphics output of an application such as a browser or spreadsheet or the pixels can be video (either live or read from a hard drive). In other applications of the servers, the server system can control output on components of the user system, and receive input from components and peripherals of the user system, all via communications over the network. Access to respective non-intelligent user systems is dictated by the master server and each higher level slave server of the hierarchical set of servers. Data representing input of components and peripherals is multiplexed and communicated over the network by the user system, and data representing output of components of the user system is received by the user system over the network and demultiplexed and delivered to the component for output on the user system.
ADAPTIVE MULTIBIT BUS FOR ENERGY OPTIMIZATION
Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.