In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.

An object is to provide a technique capable of reducing an inter-SoC communication volume. The screen generation device includes a first SoC, a second SoC, and an allocation unit. The allocation unit defines a plurality of superposition sequence layers having a superposition sequence and selected from the plurality of first drawing layers and the plurality of second drawing layers, allocates, among the plurality of superposition sequence layers, a consecutive superposition sequence layer cluster being consecutive two or more superposition sequence layers in the superposition sequence, to the first SoC, and allocates remaining superposition sequence layers being one or more superposition sequence layers other than the consecutive superposition sequence layer cluster to the second SoC.

An electronic device includes a host controller. The host controller splits a to-be-displayed image into at least two sub images, where each sub image and an adjacent sub image thereof include at least one column of overlapping image pixels. The host controller sends the at least two sub images to at least two display drive circuits, so that the at least two display drive circuits can jointly drive a display screen to display the to-be-displayed image in a sub pixel rendering (SPR) manner.

A processing system synchronizes the frequencies and phases of the display outputs of multiple video processing units (VPUs) by adjusting a local time base generated at each VPU to match a virtual global time base generated based on a network protocol and to synchronize video timing for the display outputs based on the virtual global time base.

Various embodiments disclose a system that includes a first source processor that generates a first stream of graphics data, a second source processor that generates a second stream of graphics data, a display device that displays at least one of the first stream of graphics data and the second stream of graphics data, and a timing controller that is coupled to the first source processor and the second source processor and receives a first control signal to enter into a self-refresh state, in response, enters into the self-refresh state, causes the display device to display a first frame stored in memory, wherein the first frame includes at least a portion of data included in the first stream of graphics data, receives a second stream of graphics data, exits the self-refresh state, and causes the display device to display the second stream of graphics data.

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

Methods and systems are presented for game screen rendering based on multiple graphics cards, for recognizing M physical graphics cards on a physical host, determining a rendering task and segmenting it into at least one rendering part; determining a target physical graphics card according to the at least one rendering part, wherein the target physical graphics card is one or more of the M physical graphics cards; rendering the at least one rendering part through the target physical graphics card; and outputting a rendering result through an output device.

A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Methods, systems and apparatuses may provide for technology to receive a first video data stream from a first graphics display engine via a first video data channel, receive a second video data stream from a second graphics display engine via a second video data channel, and switch a video output from the first video data stream to the second video data stream based on a switch command to accompany the second video data stream.