The liquid crystal display device includes a pixel portion including a plurality of pixels to which image signals are supplied; a driver circuit including a signal line driver circuit which selectively controls a signal line and a gate line driver circuit which selectively controls a gate line; a memory circuit which stores the image signals; a comparison circuit which compares the image signals stored in the memory circuit in the pixels and detects a difference; and a display control circuit which controls the driver circuit and reads the image signal in accordance with the difference. The display control circuit supplies the image signal only to the pixel where the difference is detected. The pixel includes a thin film transistor including a semiconductor layer including an oxide semiconductor.

This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

Various embodiments disclose a system that includes a first source processor that generates a first stream of graphics data, a second source processor that generates a second stream of graphics data, a display device that displays at least one of the first stream of graphics data and the second stream of graphics data, and a timing controller that is coupled to the first source processor and the second source processor and receives a first control signal to enter into a self-refresh state, in response, enters into the self-refresh state, causes the display device to display a first frame stored in memory, wherein the first frame includes at least a portion of data included in the first stream of graphics data, receives a second stream of graphics data, exits the self-refresh state, and causes the display device to display the second stream of graphics data.

A display driving integrated circuit (DDIC) driving a display device and including; a host interface configured to receive image data from a host device, an interface monitor configured to generate a mode signal indicating a still image mode or a video mode by detecting whether the image data from the host device is transferred through the host interface, a processing circuit configured to generate processed data by processing the image data, a conversion circuit configured to perform data conversion on the processed data to generate display data driving a display panel, and a path controller configured to store the processed data in a frame buffer and transfer the processed data stored in the frame buffer to the conversion circuit in the still image mode, and further configured to transfer the processed data to the conversion circuit without storing the processed data in the frame buffer in the video mode.

A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Processing apparatus for driving a display screen having one or more visible light pixels for outputting visible light and one or more invisible light pixels for outputting invisible light. The processing apparatus has an input for receiving video image and audio signals. A video processor processes input video image signals received at the input and provides corresponding drive signals for driving the one or more visible light pixels of the display screen to output visible light so as to display the video image. An audio processor processes input audio signals received at the input and provides corresponding drive signals for driving the one or more invisible light pixels of the display screen to output invisible light which encodes the audio.

Methods, systems and apparatuses may provide for technology that detects an immediate flip request associated with a current frame of a video signal and generates a modified frame in response to the immediate flip request, wherein the modified frame includes a plurality of scanlines containing transition content associated with the current frame and the successive frame. The technology may also send the modified frame to the display.

A display driving integrated circuit (DDIC) driving a display device and including; a host interface configured to receive image data from a host device, an interface monitor configured to generate a mode signal indicating a still image mode or a video mode by detecting whether the image data from the host device is transferred through the host interface, a processing circuit configured to generate processed data by processing the image data, a conversion circuit configured to perform data conversion on the processed data to generate display data driving a display panel, and a path controller configured to store the processed data in a frame buffer and transfer the processed data stored in the frame buffer to the conversion circuit in the still image mode, and further configured to transfer the processed data to the conversion circuit without storing the processed data in the frame buffer in the video mode.

A power supply including a first converter configured to convert an input voltage into a first output voltage; a second converter configured to convert the first output voltage into a second output voltage; a first feedback circuit configured to output a first pulse width modulation (PWM) signal to the first converter to control a level of the first output voltage; and a mode controller configured to compare the input voltage and a reference voltage and determine whether the first converter operates in a first mode or a second mode based on the compared result. When the input voltage is less than or equal to the reference voltage, the first converter boosts the input voltage and output the boosted voltage as the first output voltage in the first mode, and when the input voltage is greater than the reference voltage, the first converter bypasses the input voltage and output the bypassed voltage as the first output voltage in the second mode.

One embodiment provides a method, comprising: receiving, at an information handling device, an indication to activate a camera positioned underneath a display portion of the information handling device; identifying, using a processor, a location of at least one pixel on the display portion positioned overtop the camera; disabling, based on the identifying, the at least one pixel; performing, subsequent to the disabling and using the camera, a function; and enabling, responsive to identifying that the function was performed, the at least one pixel. Other aspects are described and claimed.