A stacked display driver integrated circuit (DDIC) configured to drive a display panel of a display device includes a first circuit and a second circuit. The first circuit is formed by a low-end process according to a first design rule such that the first circuit has a first critical dimension. The second circuit is formed by a high-end process according to a second design rule smaller than the first design rule such that the second circuit has a second critical dimension smaller than the first critical dimension. The first circuit and the second circuit are stacked in a vertical direction. The size of the stacked DDIC may be reduced by stacking, in the vertical direction, the first circuit including analog circuits and the second circuit including digital circuits.

A circuit device includes: a color reduction circuit configured to execute color reduction processing from input image data in which pixel data is m bits to color-reduced image data in which pixel data is n bits, and configured to apply spatial error diffusion or temporal error diffusion in the color reduction processing; a storage circuit storing the color-reduced image data; and an image conversion circuit configured to execute image conversion processing, which is at least one of mapping processing and scaling processing, on the color-reduced image data stored in the storage circuit to output output image data, and configured to execute interpolation processing, which is in the image conversion processing, of generating pixel data of the output image data from a plurality of pieces of pixel data of the color-reduced image data.

An organic light emitting diode display includes a data driving circuit which converts pixel data into a data voltage and supplies the data voltage to data lines during a data enable period, and senses changes in driving characteristics of a display panel within an extended vertical blank period, a scan driving circuit which supplies a scan pulse synchronized with the data voltage to scan lines during the data enable period, and outputs a scan pulse within the extended vertical blank period, and a timing controller which compensates for data of an input image using a compensation value determined based on the changes in the driving characteristics, transmits the compensated data to the data driving circuit, and controls operation timing of the data driving circuit and operation timing of the scan driving circuit.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enabling a variable refresh rate on a display. One of the methods includes receiving, from a content presentation device, a first signal set to a first value; completing generation of first visual content; and after completing the generation of the first visual content, determining that the first signal is set to the first value and a second threshold duration of time has not expired; sending, to the content presentation device, the first visual content, wherein sending the first visual content causes the content presentation device to change the first signal from the first value to the second value; and after sending the first visual content, receiving, from the content presentation device, the first signal set to the second value.

A temperature control method is provided. In the method, a terminal determines a current temperature of the terminal and determines, based on a preset corresponding relationship between a screen display frame rate and a temperature interval, a target temperature interval of the current temperature of the terminal in the preset corresponding relationship. The terminal may determine a target screen display frame rate corresponding to the target temperature interval. And the terminal may adjust a current screen display frame rate of the terminal to the target screen display frame rate, to control the temperature of the terminal to be within a preset temperature range.

A display system receives first timing information prior to the display system entering a panel self-refresh (PSR) mode. The display system supports a range of refresh rates. Prior to the display system entering the PSR mode, first timing information indicating a first refresh rate that is lower than a maximum refresh rate supported by the display system is received by the display system. The display system then refreshes images at a second refresh rate that is less than or equal to the first refresh rate using a frame stored in a buffer prior to entering the PSR mode. In some cases, the processing unit also receives second timing information from the display system in response to initiating an exit from a panel self-refresh (PSR) mode. The second timing information indicates a current scanout line that is used to schedule transmission of a subsequent frame.

In one example, an apparatus comprises a display panel having a first active mode with a first refresh rate and at least one of a first bit depth or a first brightness, and further having a second active mode with a second refresh rate and at least one of a second bit depth or a second brightness, the second refresh rate being lower than the first refresh rate, the second bit depth being lower than the first bit depth, and the second brightness being lower than the first brightness. The apparatus further comprises a controller. In response to receiving an image update request while the display panel is in the second active mode, the controller is configured to otherwise keep the display panel in the second active mode but switch the display panel to an intermediate refresh rate higher than the second refresh rate until completion of the image update request.

Methods, systems and apparatuses for processing a plurality of threads of a single-instruction multiple data (SIMD) group are disclosed. One method includes initializing a current instruction pointer of the SIMD group, initializing a thread instruction pointer for each of the plurality of threads of the SIMD group including setting a flag for each of the plurality of threads, determining whether a current instruction of the processing includes a conditional branch, resetting a flag of each thread of the plurality of threads that fails a condition of the conditional branch, and setting the thread instruction pointer for each of the plurality of threads that fails the condition of the conditional branch to a jump instruction pointer, and incrementing the current instruction pointer and each thread instruction pointer of the threads that do not fail, if at least one of the threads do not fail the condition.

A display device which can display a clear image and can display an image with low power consumption is provided. The display device includes an arithmetic circuit having a function of generating first to third display data, a first display portion, and a second display portion. The arithmetic circuit has a function of detecting a color region and a gray-scale region of the generated first display data and generating the second display data corresponding to an image to be displayed on the first display portion and the third display data corresponding to an image to be displayed on the second display portion, on the basis of the detection results.

Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.