A display controller includes a resource controller configured to receive layer information about each of a first layer and a second layer that are output at different times through a display panel during a unit frame. The display controller includes a data input direct memory access (DMA) configured to receive first image data corresponding to the first layer and second image data corresponding to the second layer, and a hardware resource configured to receive the first and second image data from the data input DMA, process the received first and second image data according to the layer information, and generate first layer data of the first layer and second layer data of the second layer. The resource controller is configured to control the data input DMA according to the layer information to determine an order in which the first and second image data are provided to the hardware resource.

Example apparatus described herein include a first circuit configured to slice an input image frame into input image slices, the first circuit including first outputs configured to output the input image slices. Described example apparatus also include digital light processing controllers (DLPCs) including first inputs coupled to the first outputs, the digital light processing controllers configured to process the input image slices to produce output image slices, the digital light processing controllers including second outputs configured to output the output image slices. Described example apparatus further include a second circuit including second inputs coupled to the second outputs, the second circuit configured to combine the output image slices to generate image frame data to provide to an input of a digital micromirror device (DMD).

A display device includes: an image display having at least one first display area and a second display area; a memory configured to store image data; and a timing controller configured to store first image data for the first display area in the memory after first image data for the first display area and the second display area is received from a host device, wherein the timing controller is configured to control the image display unit so as to display a first image in the first display area by loading the first image data for the first display area from the memory and to display a preset second image in the second display area.

The present teaching relates to method, system, medium, and implementations for data transfer in LED display. A signal signaling a timing for a next data transfer is received. In response to the signal, a next data transfer instruction is obtained that instructs reading a bit-based image block of an image from a memory. The bit-based image block is transferred, according to the next data transfer instruction, from the memory via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer. Then, the write buffer pointer is toggled to point to another of the pair of alternate buffers and the process repeats. The bit-based image blocks alternately stored in the buffers are later retrieved and displayed on the LED display.

Disclosed are systems, methods, and non-transitory computer-readable media. for reducing latency in augmented reality displays. A display controller receives, from a GPU, a stream of image pixels of a frame of virtual content to be presented on a display of a display device. The stream of image pixels is received via a high-speed bulk interface that transfers data at least as fast as can be consumed by the display. As the stream of image pixel is received, the display controller converts each respective image pixel from a data format used to transmit the stream of image pixels via the high-speed bulk interface to a data format that is compatible for display by the display. Each converted image pixel is stored in a pixel cell of the display, after which the frame is presented on the display.

An image processing method of a video device includes storing a plurality of pictures into a buffer, parsing header information of a current image of the plurality of pictures and managing a reference picture list of the current image while the current image is processed by a video engine based on the parsed header information.

Electric power consumed in display of image data is suppressed. The present invention includes: a command receiving section (10) which receives, from a host, a command indicative of whether or not an LCD (3) is to be caused to update an image displayed by the LCD (3); and a data processing section (40) carries out at least through-output or writing of the image data in a VRAM (50), with reference to (a) the command and (b) whether or not the image is to be updated in (i) a frame period in which the image data is received or (ii) a frame period coming next to the frame period.

An apparatus, method, and computer readable medium that access a frame buffer of a graphics processing unit (GPU), analyze, in the frame buffer, a frame representing displayed data, based on the analyzed frame, identify a reference patch that includes an instruction to retrieve content, generate an overlay including an augmentation layer which includes the content, superimpose the overlay onto the displayed data such that the content is viewable while a portion of the base layer is obscured, detect a user input, determine a location of the user input in the augmentation layer, associate the location in the augmentation layer with a target location in the base layer, and associate, within memory, the target location with an operation such that the user input in the augmentation layer activates an input in the base layer.

An electronic device includes a first graphic composer that composes first graphic data associated with a layer of a first composition type, a second graphic composer that composes second graphic data associated with a layer of a second composition type different from the first composition type. The electronic device also includes a processor that sets a composition type of each of a plurality of layers associated with at least one application to the first or second composition type, composes first graphic data corresponding to a layer set to the first composition type using the first graphic composer, compose the composed graphic data in the frame buffer and second graphic data corresponding to a layer set to the second composition type using the second graphic composer, and display the composed graphic data through a display connected with the electronic device.

The drive control device includes a display control part and a touch control part. The display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a display line switching cycle. The control circuit changes display and non-display drive terms in start timing on an individual display frame period basis in the first frame mode. In the second frame mode, each display frame period includes only one display drive term; the display drive term is not interrupted by a non-display drive term halfway. The second frame mode is arranged so that the cycle of the display line clock signal in synchronization with the display line switching cycle is made longer than that in the first frame mode.