A driving method of a display panel is provided, by pre-storing a new setting information of a source output enable signal in a peer-to-peer protocol, and detecting a default setting information of the source output enable signal, and according to a detection result of the default setting information, invoking the new setting information when switching different drivers, a setting information of the source output enable signal in the peer-to-peer protocol can be unified, thereby avoiding the charging time difference due to a replacement of drivers.

A display driving circuit and a display device including the same are provided. The display driving circuit includes a source driver which applies source data to a display panel, a power supply unit which receives an external voltage from a power module to generate an internal voltage and a logic unit which is supplied with the internal voltage to control the source driver, wherein the logic unit includes a voltage variable determination logic which determines whether a supply voltage including the internal voltage and the external voltage is changed, thereby generating a voltage variable signal, and a voltage control logic which receives the voltage variable signal to change the supply voltage.

Disclosed is an electronic device including a display panel displaying an image, a source driver supplying a source voltage to the display panel, and a display driver integrated circuit (DDI) including a timing controller controlling the source driver. The timing controller may be configured to identify information associated with a luminance of the image and to set a source bias current for controlling a slew rate of the source voltage based on the luminance of the image. Besides, various embodiments as understood from the specification are also possible.

A display device is provided. The device comprises a pixel array, a scanning circuit configured to select a row in the pixel array, and a signal output circuit configured to supply image signals to pixels arranged in the row selected by the scanning circuit. The device displays an image using pixels arranged between an initial line on one side in the pixel array and an end line succeeding the initial line on the other side. The scanning circuit includes a start designation circuit configured to designate the initial line, an end designation circuit configured to designate the end line and a shift register. The shift register is configured to start selection for writing the image signals from the initial line and sequentially select the rows between the initial line and the end line in one frame period for displaying one image.

The present disclosure provides a method for a display driver system and a display driver system. The method comprises: the control circuit transmitting a global signal and a first signal for a LED driver circuit in each stage to a first-stage LED driver circuit, wherein the global signal includes an command for indicating an operation mode of the LED driver circuit in each stage; the LED driver circuit in each stage determining the operation mode corresponding to the command according to the global signal, identifying a corresponding first signal of the LED driver circuit in the stage, and operating according to the determined operation mode and the corresponding first signal; and the LED driver circuit in each stage except for last stage transmitting the global signal to the LED driver circuit in its next stage, and in response to a completion of operation according to the determined operation mode and the corresponding first signal, transmitting the first signal for the LED driver circuit in each of sequential stages to the LED driver circuit in its next stage.

The present disclosure relates to a data driving device, a data processing device, and a system for driving a display device and, more particularly, it relates to a data driving device, a data processing device, and a system for smoothly performing a low-speed communication through a communication line including an alternating current coupling capacitor.

A display device includes a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel, and a timing controller configured to control the data driver, and the data driver pauses a data latch operation.

Provided is a display driving circuit including a plurality of source channels configured to provide data voltages to a plurality of data lines of a display panel, respectively; a dummy channel on one side of at least one of the source channels; and control logic configured to control operations of the source channels and the dummy channel, wherein, when failure of a first source channel from among the source channels is determined, the control logic is further configured to provide data voltages to data lines corresponding to the first source channel and second source channels, respectively, which are between the first source channel and the dummy channel, by using the second source channels and the dummy channel.

A display device includes a display panel, a display controller configured to output a video data signal, a gate driver, and a plurality of source drivers which are arranged in an extension direction of gate lines and generate a gradation voltage signal to be supplied to each of a plurality of pixel units based on the video data signal supplied from the display controller. Each of the plurality of source drivers includes a data processing unit configured to share an abnormal state sharing signal indicating whether an abnormality has occurred in communication with the display controller with other source drivers, and when the abnormal state sharing signal indicates that an abnormality has occurred in communication with the display controller, supply a gradation voltage signal corresponding to predetermined gradation data different from a gradation voltage signal based on the video data signal to each of the plurality of pixel units.

A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.