A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.

A panel control circuit for controlling a display panel comprising a first data line and a second data line includes a timing controller configured to generate input data comprising a first input data and a second input data, a first driving circuit configured to output a first video signal corresponding to the first input data into the first data line, and a second driving circuit configured to output a second video signal corresponding to the second input data into the second data line, wherein the timing controller is configured to turn off the second driving circuit based on a first deviation, a second deviation, or a third deviation.

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

A LED controller includes an image buffer to hold image data. An LED pixel forming a part of a large pixel array is activatable in response to image data, LDO state, and pulse width modulation module state. A logic module including a pixel diagnostic mode using an LDO bypass is connected to modify LDO state and allow direct addressing of the LED pixel for diagnostic purposes without needing to use image data from the image buffer.

The present application discloses a display apparatus and a drive method thereof. The display apparatus includes a display panel, and a panel chive circuit configured to drive the display panel; and a timing controller respectively transmits a signal to source drivers and a gate driver via the bus.

A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

The present invention provides a display panel and a display device. The first enable sub-signal and the second enable sub-signal output by the timing controller are modulated by the logic controller to generate a plurality of enable signals with sequentially changing phases, which can control data signals in a source driver chip to time-sharingly output by multiple sets. This reduces a load capacity of the source driver chip, which is beneficial to reducing costs of the source driver chip. The time-sharing output of the source driver chip can reduce a peak current of each output channel, thus reducing power consumption and lowering the risk of electromagnetic interference (EMI).

To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.

A video stream is encoded using spread spectrum video transport and sent as an analog signal to a display of a VR visor where a decoder integrated with a source driver decodes the analog signal and drives the display. The analog signal is sent wirelessly to the display where it is received, converted to wired format, decoded and displayed. A wireless SSVT analog signal is received at the headset processor and forwarded to the VR visor for reception, conversion, decoding and display. A wireless SSVT analog signal is received at the processor, converted to wired format, sent wirelessly to the display where it is received at a receiver, converted to wired format, decoded and displayed. A video stream is stored in persistent storage on the headset processor using SSVT encoding. The decoder integrated with a source driver of a display is implemented directly on the glass of the display panel.

Provided is a display system, including one or more display screens (11, 12), a plurality of source drivers (13, 14), a timing controller (15) and a graphics processing unit (16). Each display screen (11, 12) is connected to one or more source drivers (13, 14). The graphic processing unit (16) is connected to the timing controller (15). The timing controller (15) is connected to the plurality of source drivers (13, 14). The graphic processing unit (16) is configured to determine each image of the one or more display screens (11, 12) and transmit the image to the timing controller (15). The timing controller (15) is configured to divide each image of the one or more display screens (11, 12) into a plurality of sub-images in a P2P transmission manner, and output in parallel the corresponding sub-images to the plurality of source drivers (13, 14).